Datasheet

LMH1982
SNLS289C –APRIL 2008–REVISED MARCH 2013 www.ti.com
Pin Descriptions
(1)
Pin No. Pin Name I/O Signal Level Pin Description
– DAP – Supply Die Attach Pad (Connect to GND)
1 VC_FREERUN I Analog Free Run Control Voltage Input
2, 10, 18, 22, 26, 30 GND – Supply Ground
3, 21, 27, 28, 32 V
DD
– Supply 3.3V Supply
1
4 HREF_A I LVCMOS H sync Input, Reference A
5 VREF_A I LVCMOS V sync Input, Reference A
6 REF_SEL I LVCMOS Reference Select
2, 3
7 HREF_B I LVCMOS H sync Input, Reference B
8 VREF_B I LVCMOS V sync Input, Reference B
9 DV
DD
– Supply 2.5V Supply
4
11 SDA I/O I
2
C I
2
C Data
5
12 SCL I I
2
C I
2
C Clock
5
13 I
2
C_ENABLE I LVCMOS I
2
C Enable
14 GENLOCK I LVCMOS Mode Select
6
15 RESET I LVCMOS Device Reset
16 NO_REF O LVCMOS Reference Status Flag
17 NO_LOCK O LVCMOS Lock Status Flag
19, 20 HD_CLK, HD_CLK O LVDS HD Clock Output
23, 24 SD_CLK, SD_CLK O LVDS SD Clock Output
25 TOF O LVCMOS Top of Frame Pulse
29 VCXO I LVCMOS VCXO Clock Input
31 LPF O Analog VCXO PLL Loop Filter
(1) Notes
1. Refer to section Power Supply Sequencing.
2. To control reference selection via the REF_SEL pin instead of the I
2
C interface (default), program I
2
C_RSEL = 0 (register 00h).
3. To override reference control via pin 6 and instead use pin 6 as an logic input for output initialization, program PIN6_OVRD = 1
(register 02h); accordingly, the TOF_INIT bit (register 0Ah) will be ignored and reference selection must be controlled via I
2
C.
4. Must be ≤ V
DD
+0.3V. Refer to section Power Supply Sequencing.
5. SDA and SCL pins each require a 4.7 kΩ (typ) pull-up resistor to the V
DD
supply.
6. To control mode selection via the GENLOCK pin instead of the I
2
C interface (default), program I
2
C_GNLK = 0 (register 00h).
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)(2)
ESD Tolerance
(3)
Human Body Model 2000V
Machine Model 200V
Supply Voltage, V
DD
3.6V
Supply Voltage, DV
DD
2.75V
DV
DD
≤ V
DD
+0.3V
Input Voltage Range (any input) −0.3V to V
DD
+0.3V
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 10 sec.) 300°C
Junction Temperature, T
JMAX
150°C
Thermal Resistance (θ
JA
) 33°C/W
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
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