Datasheet

LOOP
FILTER
VCXO
LMH1982
MULTI-RATE
CLOCK GENERATOR
REF_A
REF_B
SD_CLK
HD_CLK
LPF
TOF
27 or
67.5 MHz
74.25,
74.176,
148.5, or 148.35 MHz
TX
RX_1
GENLOCKED
3G-SDI OUT
ASYNCHRONOUS
3G-SDI IN
H sync
V sync
H sync
V sync
V
C
27 MHz
FPGA
with SerDes
TRIPLE-RATE SDI
VCXO
FRAME
BUFFER
RX_2
SDI REF. IN
RECOVERED SYNC TIMING
FROM SDI REF. IN
WRITE/READ DATA and
TIMING/CLOCK SIGNALS
TOF
OPTIONAL BACK-UP
REFERENCE INPUTS
LOOP
FILTER
VCXO
LMH1982
MULTI-RATE
CLOCK GENERATOR
REF_A
REF_B
SD_CLK
HD_CLK
LPF
TOF
27 or
67.5 MHz
74.25,
74.176,
148.5 or 148.35 MHz
TX
RX_1
GENLOCKED
3G-SDI OUT
ASYNCHRONOUS
3G-SDI IN
LMH1981
MULTI-FORMAT VIDEO
SYNC SEPARATOR
H sync
V sync
ANALOG
REF. IN
H sync
V sync
V
C
27 MHz
FPGA
with SerDes
TRIPLE-RATE SDI
VCXO
FRAME
BUFFER
TOF
WRITE/READ DATA and
TIMING/CLOCK SIGNALS
OPTIONAL BACK-UP
REFERENCE INPUTS
LMH1982
SNLS289C –APRIL 2008–REVISED MARCH 2013 www.ti.com
TYPICAL SYSTEM BLOCK DIAGRAMS
Figure 15. Analog Reference Genlock for Triple-Rate SDI Video
Figure 16. SDI Reference Genlock for Triple-Rate SDI Video
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