Datasheet

LMH1982
www.ti.com SNLS289C –APRIL 2008–REVISED MARCH 2013
To minimize lock time, using a large or maximum I
CP1
can result in faster PLL settling time due to a wider loop
bandwidth. Once phase lock has been achieved, using a lower I
CP1
(that yields sufficient stability) can provide
good input jitter rejection due to a narrower loop bandwidth; this can be helpful to minimize low-frequency input
jitter from being transferred to the output clocks.
NOTE
An ICP1 value ≤ 2 corresponds to an I
CP1
current ≤ 62.5 µA. A low I
CP1
setting or low
damping factor (DF) can cause reduced PLL stability and performance (e.g. wander, loss
of lock) due to loop filter charge leakage and other secondary factors; therefore, it is not
recommended to use an ICP1 value less than 2d nor use an insufficient DF setting.
ICP1 register range = 0 to 31d; 0 to 2d are not recommended
I
CP1
current = ICP1 x 31.25 µA (nominal current step)
Examples:
ICP1 = 8d (default) gives I
CP1
= 250 µA nominal
ICP1 = 31d (max) gives I
CP1
= 968.75 µA nominal
Bits 7-5: Reserved (RSV)
These RSV bits are reserved. When writing to this register, only write the default data to the RSV bits as
specified in Table 8.
Register 14h
Bits 3-0: PLL 3 Charge Pump Current Control (ICP3)
ICP3 can be programmed to specify the charge pump current for PLL 3, which generates the 74.176 and 148.35
MHz HD clock outputs. Reducing the value of ICP3 will reduce the PLL 3 charge pump current and lower its loop
bandwidth at the expense of reduced PLL stability. An ICP3 value of 0 should not be programmed since this
corresponds to 0 µA nominal current, which will cause PLL 3 to lose phase lock or otherwise be unstable.
ICP3 register range = 0 to 15d
Bit 7-4: PLL 2 Charge Pump Current Control (ICP2)
ICP2 can be programmed to specify the charge pump current for PLL 2, which generates the 74.25 and 148.5
MHz HD clock outputs. Reducing the value of ICP2 will reduce the PLL 2 charge pump current and lower its loop
bandwidth at the expense of reduced PLL stability. An ICP2 value of 0 should not be programmed since this
corresponds to 0 µA nominal current, which will cause PLL 2 to lose phase lock or otherwise be unstable.
ICP2 register range = 0 to 15d
Reserved Registers
Register 15h-1Fh
This register is reserved. Do not program any data to these registers.
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