Datasheet
SCL
SDA
D7 D6 D5 D4 D3 D2 D1 D0D7 D6 D5 D4 D3 D2 D1 D0
1 00111011 0 0
I
2
C
Slave
Address
$DD
Data Byte 1 Data Byte n
A
C
K
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
R
e
a
d
LMH1982
SNLS289C –APRIL 2008–REVISED MARCH 2013
www.ti.com
Figure 14. LMH1982 Read Sequence – Data Read Transfer
I
2
C Enable Control Pin
When the active low input I2C_ENABLE = 0, the LMH1982 will enable I
2
C communication via its fixed slave
address; otherwise, the LMH1982 will not respond. For applications with multiple LMH1982 devices on the same
I
2
C bus, the I
2
C enable function can be useful for writing data to a specific device(s) and for reading data from an
individual device to prevent bus contention. For single chip applications, the I2C_ENABLE input can be tied to
GND to keep the I
2
C interface enabled.
I
2
C INTERFACE CONTROL REGISTER DEFINITIONS
Table 8. I
2
C Interface Control Register Map
(1)
Register Default
D7 D6 D5 D4 D3 D2 D1 D0
Address Data
00h A3h GNLK_I
2
C GNLK RSEL_I
2
C RSEL HOLD- H_ERROR [2:0]
OVER
01h 86h LOCK_CTRL [7:3] HD_LOCK SD_LOCK REF_VALID
PIN6_
02h 00h RSV RSV OVRD REF_27 POL_HA POL_VA POL_HB POL_VB
03h 01h RSV RSV RSV RSV RSV RSV REF_DIV_SEL [1:0]
04h B4h FB_DIV [7:0]
05h 06h 0 0 0 FB_DIV [12:8]
06h 00h RSV RSV RSV RSV ICP4 [3:0]
07h 00h RSV RSV RSV RSV RSV RSV RSV RSV
08h 04h RSV RSV TOF_HIZ HD_HIZ HD_FREQ [3:2] SD_HIZ SD_FREQ
09h 01h TOF_RST [7:0]
0Ah 00h EN_TOF_ POL_TOF TOF_INIT TOF_RST [12:8]
RST
0Bh B4h TOF_PPL [7:0]
0Ch 06h 0 0 TOF_CLK TOF_PPL [12:8]
0Dh 0Dh TOF_LPFM [7:0]
0Eh 02h 0 0 0 0 TOF_LPFM [11:8]
0Fh 0Dh REF_LPFM [7:0]
10h 02h 0 0 0 0 REF_LPFM [11:8]
11h 00h TOF_OFFSET [7:0]
12h 00h 0 0 0 0 TOF_OFFSET [11:8]
13h 88h RSV RSV RSV ICP1 [4:0]
14h 88h ICP2 [7:4] ICP3 [3:0]
(1) When writing to registers containing reserved bits (RSV), make sure the RSV bits are programmed with their original default data shown
in column 2 of Table 8; otherwise, improper device operation may result.
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