Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Video editing Clock generator WQFN 32 (5x5)

1

2

3

4

5

6

7

8

9

27 MHz

VCXO

LOOP

FILTER

PLL 1 with

EXT. VCXO

and LPF

PLL 2,3,4

with

INTEGRATED

VCOs

SWITCH

REFERENCE

SELECTION

and

INPUT

POLARITY

PLL LOCK

DETECT

OUTPUT TOF

TIMING

GENERATION

VC_FREERUN

LPF

VCXO

27

67.5

74.176

148.35

74.25

148.5

LVDS

REFERENCE

DETECT

SD_CLK

HD_CLK

TOF_OUT

NO_LOCK

NO_REF

H

V

TOF

CLK

REF_SEL

VREF_B

HREF_B

HREF_A

VREF_A

GENLOCK

SDA SCL

I

2

C_ENABLE

H

V

27 MHz

3

MUX

I

2

C INTERFACE and CONTROL REGISTERS

RESET

OUTPUT

RESET

SD_CLK

HD_CLK

MUX

LVDS

LOOP

FILTER

VCXO

LMH1982

MULTI-RATE

CLOCK GENERATOR

REF_A

REF_B

SD_CLK

HD_CLK

LPF

TOF

27 or

67.5 MHz

74.25,

74.176,

148.5 or 148.35 MHz

TX

RX_1

GENLOCKED

3G-SDI OUT

ASYNCHRONOUS

3G-SDI IN

LMH1981

MULTI-FORMAT VIDEO

SYNC SEPARATOR

H sync

V sync

ANALOG

REF. IN

H sync

V sync

V

C

27 MHz

FPGA

with SerDes

TRIPLE-RATE SDI

VCXO

FRAME

BUFFER

TOF

WRITE/READ DATA and

TIMING/CLOCK SIGNALS

OPTIONAL BACK-UP

REFERENCE INPUTS

LMH1982

SNLS289C –APRIL 2008–REVISED MARCH 2013

www.ti.com

Typical Video Genlock Block Diagram

Functional Block Diagram

2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated

Product Folder Links: LMH1982