Datasheet

2:1 MUX
TOF Clock Select
COUNTER 3
Reference Format
Lines per Frame
Reference
Frame Decoder
COUNTER 1
TOF Reset and
Initialization
COUNTER 2
TOF Offset
COUNTER 4
TOF Reset
COUNTER 5
Output Format
Pixels per Line
COUNTER 6
Output Format
Lines per Frame
EN_TOF_RST
0Ah[7]
TOF_INIT
0Ah[5]
Selected
VREF
input
H_FB
RST4 RST4
RST3RST3
RST1
REF CLK
TOF
output
RST4
(to PLLs 2, 3, 4)
SD_CLK
HD_CLK
TOF_OFFSET
11h-12h
REF_LPFM
0Fh-10h
TOF_RST
09h-0Ah
TOF_RST
09h-0Ah
TOF_PPL
0Bh-0Ch
TOF_LPFM
0Dh-0Eh
REF_SEL input
(pin 6)
PIN 6_OVRD
02h[5]
TOF Output Enable
and
Polarity Select
TOF_CLK
0Ch[5]
SEL
SEL
RST2
H_FB
(from PLL 1 Feedback
Divider block)
POL_TOF
0Ah[6]
TOF_HIZ
08h[5]
2:1 MUX
Init Signal Select
PLL 1 Feedback
Divider
FB_DIV
04h-05h
VCXO
input
(pin 29)
TOF/CLK Alignment Blocks
TOF Generation Blocks
RST4 (Output
Alignment Signal)
0
1
0
1
LMH1982
SNLS289C –APRIL 2008–REVISED MARCH 2013 www.ti.com
Figure 9. Functional Block Diagram – TOF Generation and Output Initialization Circuitry
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