Datasheet

LMH1982
27 MHZ
VCXO
+
-
LPF
(PIN 31)
OUT
V
C
VCXO
(PIN 29)
LMP7701
(OPTIONAL)
C
P
C
S
R
S
LOOP
FILTER
LMH1982
www.ti.com SNLS289C –APRIL 2008–REVISED MARCH 2013
The output frequency accuracy will degrade as the VCXO accuracy drifts with the decaying control voltage.
Moreover, because the H_ERROR setting (register 00h) affects the reference error threshold for LOR indication,
a higher setting for H_ERROR may result in reduced output accuracy upon LOR indication compared to when
H_ERROR = 0. For more information on programming H_ERROR, see section Programming the Loss of
Reference (LOR) Threshold.
Figure 8. Loop Filter with Optional Op Amp to Isolate VCXO's Low Input Impedance
INPUT REFERENCE
The LMH1982 features two reference ports (A and B) with H sync and V sync inputs which are used for phase
locking the outputs in Genlock mode. The reference port can be selected by programming RSEL (register 00h). If
desired, REF_SEL input can be used instead to select the reference port by initially setting I
2
C_RSEL = 0
(register 00h).
The reference signals should be 3.3V LVCMOS signals within the input voltage range specified in Electrical
Characteristics . The H sync and V sync input signals may have analog timing, such as from the LMH1981 multi-
format analog video sync separator, or digital timing, such as from an FPGA SDI deserializer.
Programming the PLL 1 Dividers
To genlock the outputs to the reference, it is necessary to phase lock the VCXO clock (PLL 1) to the H sync input
signal by programming the PLL dividers. The PLL divider values for each supported input reference format are
given in Table 1. The divider values can be determined by reducing the following ratio to its lowest integer
factors:
f
VCXO
/ f
HSYNC
= Feedback Divider / Reference Divider
where
• f
VCXO
= 27 MHz VCXO frequency
• f
HSYNC
= H sync input frequency
• Feedback Divider = 1 to 8191 (0 is invalid)
• Reference Divider = 1, 2 or 5 (1)
Table 3 shows the selection table with compatible PLL 1 reference divider values to program REF_DIV_SEL
(register 03h). The PLL 1 feedback divider value can be directly programmed to FB_DIV (register 04h-05h).
Table 3. PLL 1 Reference Divider Selection
REF_DIV_SEL
Reference Divider
Register 03h
0h 2
1h 1
2h 5
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