Datasheet

V
CC
LMH0395
V
EE
SDI
SDI
SDO1
DAP
3
4
6
13
17
18
19
8 9
11
20 21 22 24
SPI_EN
SDO1
MISO
AEC+
AEC-
MOSI
V
CC
V
CC
SCK
SS
Coaxial Cable
75:
49.9:
75:
5.6 nH
1.0 PF
1.0 PF
1.0 PF
V
CC
0.1 PF
Differential
Outputs
V
CC
0.1 PF
MUTE
REF
(SPI) SS
(SPI) MOSI
(SPI) SCK
(SPI) MISO
SDO0
14
15
SDO0
7
SDO1_ DISABLE
1
2
V
EE
5
V
EE
10
V
EE
12
16
V
EE
23
V
EE
SDO1_DISABLE
CD
CD
MUTE
REF
LMH0395
SNLS323L –AUGUST 2010–REVISED APRIL 2013 www.ti.com
APPLICATION INFORMATION
APPLICATION CIRCUIT (SPI MODE)
Figure 15 shows the application circuit for the LMH0395 in SPI mode. (Note: The application circuit shows an
external capacitor connected between the AEC+ and AEC- pins as commonly configured in legacy equalizers.
This capacitor is optional and not necessary for the LMH0395; the AEC+ and AEC- pins may be left unconnected
with no change in performance.)
Figure 15. Application Circuit (SPI Mode)
INTERFACING TO 3.3V SPI
The LMH0395 may be controlled via optional SPI register access. The LMH0395 SPI pins support 2.5V
LVCMOS logic levels and are compliant with JEDEC JESD8-5 (see DC Electrical Characteristics). Care must be
taken when interfacing the SPI pins to other voltage levels.
The 2.5V LMH0395 SPI pins may be interfaced to a 3.3V compliant SPI host by using a voltage divider or level
translator. One implementation is a simple resistive voltage divider as shown in Figure 16.
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Product Folder Links: LMH0395