Datasheet

Host
MISO
MOSI
SCK
SS
SCK
SS
LMH0395
MOSI MISO
SCK
SS
LMH0395
MOSI MISO
SCK
SS
LMH0395
MOSI MISO
SCK
SS
LMH0395
MOSI MISO
Device 1 Device 2 Device 3 Device N
LMH0395
SNLS323L –AUGUST 2010–REVISED APRIL 2013 www.ti.com
SPI Read
The SPI read is shown in Figure 5. The SPI read is 32 bits long, consisting of a 16-bit read transaction followed
by a 16-bit dummy read transaction to shift out the read data on the MISO output. The first 16-bit MOSI payload
consists of a “1” (read command), seven address bits, and eight “1”s which are ignored. The second 16-bit MOSI
payload consists of 16 “1”s which are ignored but necessary in order to shift out the requested read data on the
MISO output. The SS signal is driven low, and the first 16 bits are sent to the LMH0395's MOSI input. The prior
SPI command, address, and data are shifted out on the MISO output during the first 16-bit transaction, and are
typically ignored (this is shown as “Don't Care” on the MISO output in Figure 5. SS must return high and then is
driven low again before the second 16 bits (all “1”s) are sent to the LMH0395's MOSI input. Once again, the prior
SPI command, address, and data are shifted out on the MISO output, but this data now includes the requested
read data. The read data is available on the MISO output during the second 8 bits of the 16-bit dummy read
transaction, as shown by D7-D0 in Figure 5.
SPI Daisy-Chain Operation
The LMH0395 SPI controller supports daisy-chaining the serial data between an unlimited number of LMH0395
devices. Each LMH0395 device is directly connected to the SCK and SS pins on the host. However, only the first
LMH0395 device in the chain is connected to the host’s MOSI pin, and only the last device in the chain is
connected to the host’s MISO pin. The MISO pin of each intermediate LMH0395 device in the chain is connected
to the MOSI pin of the next LMH0395 device, creating a serial shift register. This daisy-chain architecture is
shown in Figure 9.
Figure 9. SPI Daisy Chain System Architecture
In a daisy-chain configuration of N LMH0395 devices, the host conceptually sees a shift register of length 16xN.
Therefore the length of SPI transactions (as previously described) is 16xN bits, and SS must be asserted for
16xN clock cycles for each SPI transaction.
SPI Daisy-Chain Write
Figure 10 shows the SPI daisy-chain write for a daisy-chain of N devices. The SS signal is driven low and SCK is
toggled for 16xN clocks. The 16xN bit MOSI payload (sent to Device 1 in the daisy-chain) consists of the 16-bit
SPI write data for Device N (the last device in the chain), followed by the write data for Device N-1, Device N-2,
etc., ending with the write data for Device 1 (the first device in the chain). The 16-bit SPI write data for each
device consists of a “0” (write command), seven address bits, and eight data bits. After the SPI daisy-chain write,
SS must return high and then the write occurs for all devices in the daisy-chain.
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