Datasheet

SDO0
SDO0
SDI0
SDI0
LMH0395
Coaxial Cable
75:
49.9:
75:
5.6 nH
1.0 PF
1.0 PF
SDI
SDI
LMH0356
3G/HD/SD
SDI Reclocker
100: Differential T-Line
100: Differential T-Line
SDO1
SDO1
SDI0
SDI0
LMH0356
3G/HD/SD
SDI Reclocker
SDO0
SDO0
SDI
SDI
LMH0395
Coaxial Cable
75:
49.9:
75:
5.6 nH
1.0 PF
1.0 PF
SDI
SDI
LMH0346
3G/HD/SD
SDI Reclocker
100: Differential T-Line
100:
SDO1
SDO1
SDI
SDI
LMH0346
3G/HD/SD
SDI Reclocker
100: Differential T-Line
100:
LMH0395
www.ti.com SNLS323L –AUGUST 2010–REVISED APRIL 2013
Figure 7. DC Output Interface to LMH0346 Reclocker
Figure 8. DC Output Interface to LMH0356 Reclocker
SPI Register Access
Setting SPI_EN high enables the optional SPI register access mode. In SPI mode, the LMH0395 provides
register access to all of its features along with a cable length indicator, programmable output de-emphasis,
programmable output common mode voltage and swing, digital MUTE
REF
, and launch amplitude optimization.
There are eight supported 8-bit registers in the device (see Table 1). The LMH0395 supports SPI daisy-chaining
among an unlimited number of LMH0395 devices.
SPI Transaction Overview
Each SPI transaction to a single device is 16-bits long. The transaction is initiated by driving SS low, and
completed by returning SS high. The 16-bit MOSI payload consists of the read/write command (“1” for reads and
“0” for writes), the seven address bits of the device register (MSB first), and the eight data bits (MSB first). The
LMH0395 MOSI input data is latched on the rising edge of SCK, and the MISO output data is sourced on the
falling edge of SCK.
In order to facilitate daisy-chaining, the prior SPI command, address, and data are shifted out on the MISO
output as the current command, address, and data are shifted in on the MOSI input. For SPI writes, the MISO
output is typically ignored as “Don't Care” data. For SPI reads, the MISO output provides the requested read data
(after 16 periods of SCK). The MISO output is active when SS low, and tri-stated when SS is high.
SPI Write
The SPI write is shown in Figure 4. The SPI write is 16 bits long. The 16-bit MOSI payload consists of a “0” (write
command), seven address bits, and eight data bits. The SS signal is driven low, and the 16 bits are sent to the
LMH0395's MOSI input. After the SPI write, SS must return high. The prior SPI command, address, and data
shifted out on the MISO output during the SPI write is shown as “Don't Care” on the MISO output in Figure 4.
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