Datasheet

9.76 k:
3.16 k:
MOSI
SCK
SS
3.16 k:
3.16 k:
LMH0394
3.3V
Compliant
SPI Host
9.76 k:
9.76 k:
MISO
LMH0394
www.ti.com SNLS312L –AUGUST 2010–REVISED APRIL 2013
INTERFACING TO 3.3V SPI
The LMH0394 may be controlled via optional SPI register access. The LMH0394 SPI pins support 2.5V
LVCMOS logic levels and are compliant with JEDEC JESD8-5 (see DC Electrical Characteristics). Care must be
taken when interfacing the SPI pins to other voltage levels.
The 2.5V LMH0394 SPI pins may be interfaced to a 3.3V compliant SPI host by using a voltage divider or level
translator. One implementation is a simple resistive voltage divider as shown in Figure 14.
Figure 14. 3.3V SPI Interfacing
CROSSTALK IMMUNITY
Single-ended SDI signals are susceptible to crosstalk and good design practices should be employed to
minimize its effects. Most crosstalk originates through capacitive coupling from adjacent signals routed closely
together via traces and connectors. To reduce capacitive coupling, SDI signals should be appropriately spaced
apart or insulated from one another. This can be accomplished by physically isolating signal traces in the layout
and by providing additional ground pins between signal traces in connectors as necessary. These techniques
help to reduce crosstalk but do not eliminate it.
The LMH0394 was designed specifically with crosstalk in mind and incorporates advanced circuit design
techniques that help to isolate and minimize the effects of cross-coupling in high-density system designs. Lab
evaluations and customer testimonials have shown other adaptive cable equalizers are much more susceptible to
crosstalk, resulting in significant cable reach degradation. The LMH0394’s enhanced design results in minimal
degradation in cable reach in the presence of crosstalk and overall superior immunity against cross-coupling
from neighboring channels.
PCB LAYOUT RECOMMENDATIONS
For information on layout and soldering of the WQFN package, pease refer to the following application note: AN-
1187 Leadless Leadframe Package (LLP) application report (literature number SNOA401).
The SMPTE 424M, 292M, and 259M standards have stringent requirements for the input return loss of receivers,
which essentially specify how closely the input must resemble a 75Ω network. Any non-idealities in the network
between the BNC and the equalizer will degrade the input return loss. Care must be taken to minimize
impedance discontinuities between the BNC and the equalizer to ensure that the characteristic impedance of this
trace is 75Ω. Please consider the following PCB recommendations:
• Use surface mount components, and use the smallest components available. In addition, use the smallest
size component pads.
• Select trace widths that minimize the impedance mismatch between the BNC and the equalizer.
• Select a board stack up that supports both 75Ω single-ended traces and 100Ω loosely-coupled differential
traces.
• Place return loss components closest to the equalizer input pins.
• Maintain symmetry on the complimentary signals.
• Route 100Ω traces uniformly (keep trace widths and trace spacing uniform along the trace).
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