Datasheet

LMH0384
www.ti.com SNLS308F –APRIL 2009–REVISED APRIL 2013
PIN DESCRIPTIONS – Pin Mode (non-SPI) / SPI_EN = GND / LMH0344 Compatible (continued)
Pin Name I/O, Type Description
5 AEC+ I/O, Analog AEC loop filter external capacitor (1µF) positive connection.
6 AEC- I/O, Analog AEC loop filter external capacitor (1µF) negative connection.
7 BYPASS I, LVCMOS Equalization bypass. This pin has an internal pulldown.
H = Equalization is bypassed (no equalization occurs).
L = Normal operation.
8 MUTE
REF
I, Analog Mute reference input. Sets the threshold for CD and (with CD tied to MUTE) determines the
maximum cable to be equalized before muting. MUTE
REF
may be either unconnected or
connected to ground for normal CD operation.
9 V
EE
I, LVCMOS Connect this pin to ground or drive it logic low.
10 SDO O, LVDS Serial data complement output.
11 SDO O, LVDS Serial data true output.
12 AUTO SLEEP I, LVCMOS Auto Sleep. AUTO SLEEP has precedence over MUTE and BYPASS. This pin has an
internal pullup.
H = Device will power down when no input is detected.
L = Normal operation (device will not enter auto power down).
13 V
CC
Power Positive power supply (+3.3V).
14 MUTE I, LVCMOS Output mute. CD may be tied to this pin to inhibit the output when no input signal is present.
MUTE has precedence over BYPASS. This pin has an internal pulldown.
H = Outputs forced to a muted state.
L = Outputs enabled.
15 CD O, LVCMOS Carrier detect.
H = No input signal detected.
L = Input signal detected.
16 V
CC
Power Positive power supply (+3.3V).
DAP V
EE
Ground Connect exposed DAP to negative power supply (ground).
PIN DESCRIPTIONS – SPI Mode / SPI_EN = V
CC
Pin Name I/O, Type Description
1 V
EE
Ground Negative power supply (ground).
2 SDI I, SDI Serial data true input.
3 SDI I, SDI Serial data complement input.
4 SPI_EN I, LVCMOS SPI register access enable. This pin has an internal pulldown.
H = SPI register access mode.
L = Pin mode.
5 AEC+ I/O, Analog AEC loop filter external capacitor (1µF) positive connection.
6 AEC- I/O, Analog AEC loop filter external capacitor (1µF) negative connection.
7 CD O, LVCMOS Carrier detect.
H = No input signal detected.
L = Input signal detected.
8 MUTE
REF
I, Analog Mute reference input. Sets the threshold for CD and (with CD tied to MUTE) determines the
maximum cable to be equalized before muting. MUTE
REF
may be either unconnected or
connected to ground for normal CD operation.
9 SS (SPI) I, LVCMOS SPI slave select. This pin has an internal pullup.
10 SDO O, LVDS Serial data complement output.
11 SDO O, LVDS Serial data true output.
12 MISO (SPI) O, LVCMOS SPI Master Input / Slave Output. LMH0384 data transmit.
13 V
CC
Power Positive power supply (+3.3V).
14 SCK (SPI) I, LVCMOS SPI serial clock input.
15 MOSI (SPI) I, LVCMOS SPI Master Output / Slave Input. LMH0384 data receive.
16 V
CC
Power Positive power supply (+3.3V).
DAP V
EE
Ground Connect exposed DAP to negative power supply (ground).
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Product Folder Links: LMH0384