Datasheet

SDO
SDO
SDI0
SDI0
LMH0384
Coaxial Cable
75:
37.4:
75:
5.6 nH
1.0 PF
1.0 PF
SDI
SDI
LMH0356
3G/HD/SD
SDI Reclocker
100: Differential T-Line
SDO
SDO
SDI
SDI
LMH0384
Coaxial Cable
75:
37.4:
75:
5.6 nH
1.0 PF
1.0 PF
SDI
SDI
LMH0346
3G/HD/SD
SDI Reclocker
100: Differential T-Line
100:
LMH0384
SNLS308F –APRIL 2009–REVISED APRIL 2013 www.ti.com
The LMH0384 allows flexibility when interfacing to low voltage crosspoint switches (i.e. 1.8V) and other devices
with limited input ranges. The LMH0384 outputs can be DC coupled to these devices in most cases, avoiding the
need to AC couple.
The LMH0384 may be AC coupled to the receiving device when necessary. For example, the LMH0384 outputs
are not strictly compatible with 3.3V CML and thus should not be connected via 50Ω resistors to 3.3V. If the input
common mode range of the receiving device is not compatible with the output common mode range of the
LMH0384, then AC coupling is required. Following the AC coupling capacitors, the signal may have to be biased
at the input of the receiving device.
Figure 5. DC Output Interface to LMH0346 Reclocker
Figure 6. DC Output Interface to LMH0356 Reclocker
SPI REGISTER ACCESS
Setting SPI_EN high enables the optional SPI register access mode. In SPI mode, the LMH0384 provides
register access to all of its features along with a cable length indicator, programmable output common mode
voltage and swing, and launch amplitude optimization. There are five supported 8-bit registers in the device (see
Table 1). With SPI_EN set low, the device operates in pin mode and is footprint compatible with the LMH0344,
LMH0044, and LMH0074.
SPI WRITE
The SPI write is shown in Figure 2. The MOSI payload consists of a “0” (write command), seven address bits,
and eight data bits. The SS signal is driven low, and the 16 bits are sent to the LMH0384's MOSI input. Data is
latched on the rising edge of SCK. The MISO output is normally tri-stated during this operation. After the SPI
write, SS must return high.
SPI READ
The SPI read is shown in Figure 3. The MOSI payload consists of a “1” (read command) and seven address bits.
The SS signal is driven low, and the eight bits are sent to the LMH0384's MOSI input. The addressed location is
accessed immediately after the rising edge of the 8
th
clock and the eight data bits are shifted out on MISO
starting with the falling edge of the 8
th
clock. MOSI must be tri-stated immediately after the rising edge of the 8
th
clock. After the SPI read, SS must return high.
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Product Folder Links: LMH0384