Datasheet
LMH0356
www.ti.com
SNLS270K –AUGUST 2007–REVISED APRIL 2013
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.
(1)
Symbol Parameter Conditions Reference Min Typ Max Units
BR
SD
Serial Data Rate SMPTE 259M, C SDI, SDO 270 Mbps
BR
SD
Serial Data Rate SMPTE 292M 1483,
Mbps
1485
BR
SD
Serial Data Rate SMPTE 424M 2967,
Mbps
2970
TOL
JIT
Serial Input Jitter Tolerance 270 Mbps SDI
>6 UI
P-P
(2) (3) (4)
TOL
JIT
Serial Input Jitter Tolerance 270 Mbps
>0.6 UI
P-P
(2) (3) (5)
TOL
JIT
Serial Input Jitter Tolerance 1483 or 1485 Mbps
>6 UI
P-P
(2) (3) (4)
TOL
JIT
Serial Input Jitter Tolerance 1483 or 1485 Mbps
>0.6 UI
P-P
(2) (3) (5)
TOL
JIT
Serial Input Jitter Tolerance 2967 or 2970 Mbps
>6 UI
P-P
(2) (3) (4)
TOL
JIT
Serial Input Jitter Tolerance 2967 or 2970 Mbps
>0.6 UI
P-P
(2) (3) (5)
t
JIT
Serial Data Output Jitter 270 Mbps
(3) (6)
SDO 0.01 0.03 UI
P-P
t
JIT
Serial Data Output Jitter 1483 or 1485 Mbps
0.04 0.05 UI
P-P
(3) (7)
t
JIT
Serial Data Output Jitter 2967 or 2970 Mbps
0.08 0.09 UI
P-P
(3) (8)
BW
LOOP
Loop Bandwidth 270 Mbps,
275 kHz
<0.1dB Peaking
1485 Mbps,
1.5 MHz
<0.1dB Peaking
2970 Mbps,
2.75 MHz
<0.1dB Peaking
F
CO
Serial Clock Output 270 Mbps data rate SCO
270 MHz
Frequency
F
CO
Serial Clock Output 1483 Mbps data rate
1483 MHz
Frequency
F
CO
Serial Clock Output 1485 Mbps data rate
1485 MHz
Frequency
F
CO
Serial Clock Output 2967 Mbps data rate
2967 MHz
Frequency
F
CO
Serial Clock Output 2970 Mbps data rate
2970 MHz
Frequency
t
JIT
Serial Clock Output Jitter 2 3 ps
RMS
Serial Clock Output
(3)
SDO, SCO
Alignment with respect to 40 60 %
Data Interval
Serial Clock Output Duty
(3)
SCO
45 55 %
Cycle
T
ACQ
Acquisition Time
(9)
15 ms
t
r
, t
f
Input rise/fall time 10%–90% Logic inputs 1.5 ns
(1) Typical values are stated for: V
CC
= +3.3V, T
A
= +25°C.
(2) Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars.
(3) This parameter is ensured by characterization over voltage and temperature limits.
(4) Refer to “A1” in Figure 1 of SMPTE RP 184-1996.
(5) Refer to “A2” in Figure 1 of SMPTE RP 184-1996.
(6) PRBS 2
10
– 1, input jitter = 31 ps
P-P
.
(7) PRBS 2
10
– 1, input jitter = 24 ps
P-P
.
(8) PRBS 2
10
– 1, input jitter = 22 ps
P-P
.
(9) Measured from first SDI transition until Lock Detect output goes high (true).
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