Datasheet
LMH0356
SDI0
SDI0
1
2
3
4
5
6
7
8
9
10
11
12
SCO_EN
25
26
27
28
29
30
31
32
33
34
SCO/SDO2
SCO/SDO2
SDO
SDO
HD
SD/
13
14
15
16
17
18
19
20
21
22
V
CC
SDI1
SDI1
V
CC
SDI2
SDI2
SDI3
SDI3
ENABLE
V
EE
V
CC
V
CC
MUTE
XTAL IN/EXT CLK
BP/
AUTO BP
V
EE
V
EE
V
EE
V
EE
XTAL OUT
LOCK DET
23
24
V
EE
V
EE
V
EE
V
EE
35
36
V
CC
V
CC
V
CC
V
CC
37
38
39
40
41
42
43
44
45
46
47
48
DAP
V
EE
V
EE
V
EE
V
EE
V
EE
SEL1
SEL0
RATE1
RATE0
LF2
LF1
Differential
Data Input 3
V
CC
Differential
Data Input 2
Differential
Data Input 1
Differential
Data Input 0
ENABLE
V
CC
27 MHz
39 pF 39 pF
Data
Output
Clock Output or
2
nd
Data Output
HD
SD/
V
CC
56 nF
LOCK DET
MUTE
BYPASS/
AUTO BP
SEL1
SEL0
RATE1
RATE0
SCO_EN
OP
OP
LMH0356
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SNLS270K –AUGUST 2007–REVISED APRIL 2013
APPLICATION INFORMATION
Figure 6 shows a typical application circuit for the 48-pin WQFN version of the LMH0356.
Figure 6. Application Circuit
ENABLE has an internal pullup to enable the device by default. This pin may be pulled low to put the LMH0356
into a powered down mode.
BYPASS/AUTO BYPASS has an internal pulldown to enable Auto Bypass mode by default. This pin may be
pulled high to force the LMH0356 to bypass all data.
OUTPUT MUTE has an internal pullup to enable the outputs by default. This pin may be pulled low to mute the
outputs.
The XTAL IN/EXT CLK and XTAL OUT pins are shown with a 27 MHz crystal and the proper loading. The crystal
should match the parameters described in Table 4. Alternately, a 27MHz LVCMOS compatible clock signal may
be input to XTAL IN/EXT CLK.
The active high LOCK DETECT output provides an indication that proper data is being received and the PLL is
locked.
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