Datasheet

RXCLKOUT
80%
20%
t
ROTR
80%
20%
t
ROTF
DVBC
t
DVAC
t
DVBC
t
DVAC
t
RX[4:0]
ROCH
t
ROCL
t
LMH0041, LMH0051
LMH0071, LMH0341
www.ti.com SNLS272Q –APRIL 2007–REVISED APRIL 2013
LVDS Switching Characteristics
Over supply and Operating Temperature ranges unless otherwise specified.
(1)
Symbol Parameter Condition Min Typ Max Units
t
ROTR
LVDS Low to High Transition time See Figure 3 LVDS Switching 300 ps
times
t
ROTF
LVDS High to Low Transition time 300 ps
t
ROCP
Receiver output clock period RxCLKOUT is DDR. If divide by 2T ns
4 is enabled, the output clock
period will be doubled
t
RODC
RxCLKOUT Duty Cycle 45 50 55 %
t
ROCH
RxCLKOUT high time See Receiver timing 1.51 ns
specifications
t
ROCL
RxCLKOUT low time 1.51 ns
t
RBIT
Receiver output bit width T ns
t
DVBC
RX data transition to RXCLK transition See Receiver timing 650 ps
specifications
(2)
t
DVAC
RXCLK transition to RX data transition 650 ps
t
ROJR
Receiver output Random Jitter Receiver output intrinsic random 2.5 ps
jitter. Bit error rate ≤ 10
-15
.
Alternating 10 pattern. RMS
(3)
t
ROJT
Peak-to-Peak Receiver Output Jitter
(3)
70 125 ps
t
RD
Receiver Propagation Delay See Figure 5 Receiver (LVDS 12 T
Interface) Propagation Delay
t
RLA
Receiver Link Acquisition Time From device reset or change in 24 ms
input data rate to locked
condition
t
LVSK
LVDS Output Skew LVDS Differential Output Skew 20 ps
between + and − pins
(1) Typical Parameters measured at V
DD
=3.3V, T
A
=25°C. They are for reference purposes and are not production tested.
(2) Specification Characterized at 2.97 Gbps, 1.485 Gbps and 270 Mbps, production tested at 270 Mbps only
(3) Specification ensured by characterization
Figure 3. LVDS Switching Times
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Product Folder Links: LMH0041 LMH0051 LMH0071 LMH0341