Datasheet

LMH0041, LMH0051
LMH0071, LMH0341
www.ti.com SNLS272Q –APRIL 2007–REVISED APRIL 2013
Table 2. DES Register Detail Table (continued)
ADD 'h Name Bits Field R/W Default Description
22 Override This register allows the user to control the DVB_ASI and input select functions via the SMBus interface rather
than the pin controls.
7:5 Reserved
4 RX_MUX r/w 0 Writing a '1' to this register allows register 21 to control
Control Override the state of the input multiplexer — if the bit is set to '0'
then the selection will be determined by the state of the
RX_MUX_SEL pin
3:1 Reserved
0 DVB_ASI Writing a '1' to this register allows register 21 to control
Override the state of the DVB_ASI Select pin — if the bit is set to
'0' then the selection will be determined by the state of the
DVB_ASI pin if '1' then the contents of register 21 take
precidence
23–26 Reserved
27 LVDS Control 1 This register allows control of the LVDS output pins — using this register individual LVDS outputs can be
enabled or disabled, and the outputs can be switched to high output mode
7 LVDS_VOD r/w 0 With a '0' the V
OD
of the LVDS output are as described in
Electrical Characteristics, writing a '1' to this bit generates
a larger V
OD
allowing longer traces to be driven, and
increasing total power dissipation
6 LVDS Control r/w 0 Writing a '1' to this bit allows the LVDS outputs to be
controlled via the SMBus
5 RXCLK Enable r/w 0 Enables the RXCLK output driver
4 RX4 Enable r/w 0 Enables RX4 output driver
3 RX3 Enable r/w 0 Enables RX3 output driver
2 RX2 Enable r/w 0 Enables RX2 output driver
1 RX1 Enable r/w 0 Enables RX1 output driver
0 RX0 Enable r/w 0 Enables RX0 output driver
28 LVDS Control 2 More bits allowing control over the LVDS outputs
7 Reserved
6 LVDS Reset r/w 0 Resets LVDS Block
5 RXCLK Rate r/w 1 1: RXCLK is a DDR clock
0: RXCLI is at a rate of DDR/2
4 RXCLK Invert r/w 0 Inverts the polarity of the RXCLK signal
3:2 LVDS Clock r/w 10'b Each LSB adds 80ps delay to the RXCLK signal path,
delay allowing the setup and hold times to be adjusted.
1:0 Reserved
29–2A Reserved
2B Event Allows control over the counting of error events on the clock recovery PLL
Configuration
7:4 Reserved
3 Event Count r/w 0 0: Select CDR Event counter for reading — events are
Select counted for a loss of the RXCLK signal, or a loss of lock
1: Select data event counter
2 Reset CDR r/w 0 Resets CDR Event count
Error Count
1 Reset Link Error r/w 0 resets data event counter
Count
0 enable count r/w 0 enables event counters
2C Reserved
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Product Folder Links: LMH0041 LMH0051 LMH0071 LMH0341