Datasheet

LMH0041, LMH0051
LMH0071, LMH0341
www.ti.com SNLS272Q –APRIL 2007–REVISED APRIL 2013
REGISTER DESCRIPTIONS
Table 2 provides details on the device's configuration registers.
Table 2. DES Register Detail Table
ADD 'h Name Bits Field R/W Default Description
00 device_identificati The seven MSBs of this register define the SMBus address for the device. The default value is 0x58h, but this
on may be overwritten. The LSB of this register must always be '0' Note that since the address is shifted over by
one bit, some systems may address the 058h as 'B0h
7:1 device_id r/w 058h SMBus Device ID
0 reserved 0
01 reset If a '1' is written into the LSB of register 0x01h then the device will do a soft reset, restoring it's internal state
to the same as at powerup with the exception of the contents of register 0x00h, which if modified will remain
unchanged
7:1 reserved
0 sw_rst r/w 0'b Software Reset
02 GPIO_0 This register configures GPIO_0. Note, if this pin is to be used as an input, then the output must be TRI-
Configuration STATE (bit[0]=’0’) and if used as an output, then the input buffer must be disabled (bit[1]=’0’).
7:4 GPIO_0_mode[3 r/w 0000'b 0000: GPout register
:0] 0001: signal detect 0
all others: reserved
3:2 GPIO_0_ren[1:0 r/w 01'b 00: pullup and pulldown disabled
] 01: pulldown enabled
10: pullup enabled
11: Reserved
1 GPIO_0_sleepz r/w 0'b 0: input buffer disabled
1: input buffer enabled
0 GPout0 enable r/w 1'b 0: output TRI-STATE
1: output enabled
03 GPIO_1 This register configures GPIO_1. Note, if this pin is to be used as an input, then the output must be TRI-
Configuration STATE (bit[0]=’0’) and if used as an output, then the input buffer must be disabled (bit[1]=’0’).
7:4 GPIO_0_mode[3 r/w 0000'b 0000: POR
:0] 0001: GP_OUT[1]
0010:signal detect 1
0011:cdr_lock
all others: reserved
3:2 GPIO_0_ren[1:0 r/w 01'b 00: pullup and pulldown disabled
] 01: pulldown enabled
10: pullup enabled
11: Reserved
1 GPIO_0_sleepz r/w 0'b 0: input buffer disabled
1: input buffer enabled
0 GPout0 enable r/w 1'b 0: output TRI-STATE
1: output enabled
04 GPIO_2 This register configures GPIO_2. Note, if this pin is to be used as an input, then the output must be TRI-
Configuration STATE (bit[0]=’0’) and if used as an output, then the input buffer must be disabled (bit[1]=’0’).
7:4 GPIO_0_mode[3 r/w 0000'b 0000: GPout [2]register
:0] 0001:Always ON clock
0010: LVDS TX CLK
0011:CDR_CLK
all others: reserved
3:2 GPIO_0_ren[1:0 r/w 01'b 00: pullup and pulldown disabled
] 01: pulldown enabled
10: pullup enabled
11: Reserved
1 GPIO_0_sleepz r/w 0'b 0: input buffer disabled
1: input buffer enabled
0 GPout0 enable r/w 1'b 0: output TRI-STATE
1: output enabled
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Product Folder Links: LMH0041 LMH0051 LMH0071 LMH0341