Datasheet

-60
-50
-40
-30
-20
-10
0
1.00E+07 1.00E+08 1.00E+09 1.00E+10
RETURN LOSS (dB)
SMPTE 424 Limit
Measured Evaluation
Board Return Loss
FREQUENCY
LMH0041, LMH0051
LMH0071, LMH0341
SNLS272Q –APRIL 2007–REVISED APRIL 2013 www.ti.com
Figure 16. Evaluation Board Loopthrough Output Return Loss
TYPICAL SMPTE APPLICATIONS CIRCUIT
A typical application circuit for the DES is shown in Figure 17. This circuit shows the LMH0341 3 Gbps
deserializer, alternately this could employ the LMH0041 or LMH0071 deserializers in lower data rate SMPTE
applications.
The RX interface between the DES and the host FPGA is composed of a 5-bit LVDS Data bus and its LVDS
clock. This is a point-to-point interface. Line termination should be provided by the FPGA device. If not, and
external 100Ω resistor maybe used and should be located as close to the FPGA as possible to minimize stub
lengths. Pairs should be of equal length to minimize any skew impact. The LVDS clock (RXCLK) uses both
edges to transfer the data.
An SMBus is also connected from the host FPGA to the DES. If the SMBus is shared, a chip select signal is
used to select the device being addressed. The SCK and SDA signals require a pull up resistor. The SMB_CS is
driven by a GPO signal from the FPGA. Depending on the FPGA I/O it may also require a pull up unless it is a
push / pull output.
Depending upon the application, several other Host GPIO signals maybe used. This includes the DVB_ASI and
RESET input signals. If these pins are not used, then must be tied off to the desired state. The LOCK signal
maybe used to monitor the DES. If it is unused, leave the pin as a NC (or route to a test point).
Note also in this circuit, the LMH0341 GPIO_1 pin has been configured to provide the status of RXIN_1. When
there is a signal present coming from the LMH0340, then RXIN_1 will be selected. If that signal is lost, the input
MUX will automatically switch over to provide the system reference black signal as the input from RXIN_0.
The DES includes a SMPTE compliant cable driver for the Loopthrough function. While this is a differential driver,
it is commonly used single-endedly to drive 75 Ω coax cables. External 75 Ω pull up resistors are used to the
2.5V rail. The active output(s) also includes a matching network to meet the required Output Return Loss SMPTE
specification. While application specific, in general a series 75 Ω resistor shunted by a 6.8 nH inductor will
provide a starting value to design with. The signal is then AC coupled to the cable with a 4.7 µF capacitor. If the
complementary output is not used, simply terminate it after its AC coupling capacitor to ground. This output (even
though its inverting) may still be used for a loop back or 1:2 function due to the nature of the NRZI coding that
the SMPTE standards require. The output voltage amplitude of the cable driver is set by the R
SET
resistor. For
single-ended applications, an 7.87kΩ resistor is connected between this pin and ground to set the swing to
800mV.
The PLL loop filter is external for the SER. A capacitor is connected between the LF_CP and LF_REF pins.
Typical value is 30 nF.
There are several configuration pins that requiring setting to the proper level. The RSVD_H pins should be pulled
High to the 3.3V rail with a 5 kΩ resistor. Depending upon the application the DVB_ASI pin may be tied off or
driven.
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Product Folder Links: LMH0041 LMH0051 LMH0071 LMH0341