Datasheet

LMH0041, LMH0051

LMH0071, LMH0341

www.ti.com

SNLS272Q –APRIL 2007–REVISED APRIL 2013

APPLICATION INFORMATION

PCB LAYOUT RECOMMENDATIONS

In almost all applications, the inputs to the DES will be driven by the output of an equalizer such as the

LMH0044. You should follow the recommendations on the equalizer datasheet for the interface between the

input connector and the equalizer—the DES will be placed between the equalizer and the FPGA. If the DES is

too close to the equalizer, then there is a risk of crosstalk between the high speed digital outputs of the DES and

the equalizer inputs. Conversely, if too far away then the interconnect between the equalizer and the DES may

either pick up stray noise, or may broadcast noise since this is a very high speed signal. Be certain to treat the

signal from the equalizer to the DES as a differential trace. If there is skew between the two conductors of the

differential trace, not only might this cause difficulties for the DES receive circuitry, but having a phase difference

between the sides of the pair makes the signal look and radiate like a common mode signal.

If the loopthrough output is going to be used, it is advised that the DES be placed close to the Loopthrough

output BNC connector, and the equalizer be placed close to the SDI Input BNC connector. This will minimize the

lengths of the most critical connections.

The DES includes a cable driver for the loopthrough output. The SMPTE Serial specifications have very stringent

requirements for output return loss on drivers. The output return loss will be degraded by non-idealities in the

connection between the DES and the output connector. All efforts should be taken to minimize the trace lengths

for this area, and to assure that the characteristic impedance of this trace is 75Ω. The 75Ω termination resistor

should be placed as close to the loopthrough output pin as is practicable.

It is recommended that the PCB traces between the host FPGA and the DES be no longer than 10 inches

(25cm) and that the traces be routed as differential pairs, with very tight matching of line lengths and coupling

within a pair, as well as equal length traces for each of the six pairs.

PCB DESIGN DO’S AND DON’TS

DO Whenever possible dedicate an entire layer to each power supply whenever possible—this will reduce the

inductance in the supply plane.

DO use surface mount components whenever possible.

DO place bypass capacitors close to each power pin.

DON’T create ground loops—pay attention to the cutouts that are made in your power and ground planes to

make sure that there are not opportunities for loops.

DON’T allow discontinuities in the ground planes—return currents will follow the path of least resistance—for

high frequency signals this will be the path of least inductance.

DO place the Loopthrough outputs as close as possible to the edge of the PCB where it will connect to the

outside world.

DO make sure to match the trace lengths of all differential traces, both between the sides of an individual pair,

and from pair to pair.

DO remember that VIAs have significant inductance—when using a via to connect to a power supply or ground

layer, two in parallel are better than one.

DO connect the slug on the bottom of the package to a solid Ground connection. This contact is used for the

major GND connection to the device as well as serving as a thermal via to keep the die at a low operating

temperature.

Product Folder Links: LMH0041 LMH0051 LMH0071 LMH0341