Datasheet

FPGA
Host
LVCMOS GPIO
SMBus Interface
3V3
SCK SDA SMB_CS
SMBus
Device
SCK SDA SMB_CS
SMBus
Device
SCK SDA SMB_CS
SMBus
Device
3V3
3V3
3V3
FPGA
Host
LVCMOS GPIO
SMBus Interface
3V3
SCK SDA SMB_CS
SMBus
Device
SCK SDA SMB_CS
SMBus
Device
SCK SDA SMB_CS
SMBus
Device
LMH0041, LMH0051
LMH0071, LMH0341
www.ti.com SNLS272Q –APRIL 2007–REVISED APRIL 2013
Figure 12. SMBus Configuration 2 — Host to multiple devices with SMB_CS signals
Figure 13. SMBus Configuration 3 — Host to multiple devices with multiple SMBus Interfaces
GENERAL PURPOSE I/O PINS (GPIO)
The DES has three pins which can be configured to provide direct access to certain register values via a
dedicated pin. For example if a particular application required fast action to the condition of the deserializer losing
it’s input signal, the PCLK detect status bit could be routed directly to an external pin where it might generate an
interrupt for the host processor. GPIO pins can be configured to be in TRI-STATE
®
(High Impedance) mode, the
buffers can be disabled, and when used as inputs can be configured with a pullup resistor, a pulldown resistor or
no input pin biasing at all.
Each of the GPIO pins has a register to control it. For each of these registers, the upper 4 bits are used to define
what function is desired of the GPIO pin with options being slightly different for each of the three GPIO pins. The
pins can be used to monitor the status of various internal states of the LMH0040 device, to serve as an input
from some external stimulus, and for output to control some external function.
GPIO
0
Functions
• Allow for the output of a signal programmed by the SMBus
• Allow the monitoring of an external signal via the SMBus
• Monitor the status of the signal on input 0
GPIO
1
Functions
• Monitor Power On Reset
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Product Folder Links: LMH0041 LMH0051 LMH0071 LMH0341