Datasheet

FPGA
Host
LVCMOS GPIO
SMBus Interface
3V3
SCK SDA SMB_CS
SMBus
Device
3V3
LMH0041, LMH0051
LMH0071, LMH0341
SNLS272Q –APRIL 2007–REVISED APRIL 2013 www.ti.com
Transfer Of Data To The Device Via The SMBus
During normal operation the data on SDA must be stable during the time when SCK is high.
START / STOP / IDLE conditions—
There are three unique states for the SMBus:
START A HIGH to LOW transition on SDA while SCK is high indicates a message START condition,
STOP A LOW to HIGH transition on SDA while SCK is high indicates a message STOP condition.
IDLE If SCK and SDA are both high for a time exceeding t
BUF
from the last detected STOP condition or if they
are high for a total exceeding the maximum specification for t
HIGH
then the bus will transfer to the IDLE
state.
SMBus Transactions
A transaction begins with the host placing the DES SMBus into the START condition, then a byte (8 bits) is
transferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’ to signify an ACK, or ‘1’ to signify NACK, after
this the host holds the SCL line low, and waits for the receiver to raise the SDA line as an ACKnowledge that the
byte has been received.
WRITING TO REGISTERS VIA THE SMBus INTERFACE
To write a data value to a register in the DES, the host writes three bytes, the first byte is the device
address—the device address is a 7 bit value, and if writing to the DES the last bit (LSB) is set to ‘0’ to signify that
the operation is a write. The second byte written is the register address, and the third byte written is the data to
be written into the addressed register. If additional data writes are performed, the register address is
automatically incremented. At the end of the write cycle the host places the bus in the STOP state.
READING FROM REGISTERS VIA THE SMBus INTERFACE
To read the data value from a register, first the host writes the device address with the LSB set to a ‘0’ denoting
a write, then the register address is written to the device. The host then reasserts the START condition, and
writes the device address once again, but this time with the LSB set to a ‘1’ denoting a read, and following this
the DES will drive the SDA line with the data from the addressed register. The host indicates that it has finished
reading the data by asserting a ‘1’ for the ACK bit. After reading the last byte, the host will assert a ‘0’ for NACK
to indicate to the DES that it does not require any more data.
Figure 11. SMBus Configuration 1 — Host to single device
16 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH0041 LMH0051 LMH0071 LMH0341