Datasheet

2.5V

TXOUT+

TXOUT-

24 mA

LMH0041, LMH0051

LMH0071, LMH0341

SNLS272Q –APRIL 2007–REVISED APRIL 2013

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PLL will lose lock, and then reacquire lock. This condition can be seen by monitoring the LOCK pin where a high

going pulse will indicate a loss of lock condition. If a loss of lock happens, it will be for a time period of

approximately 5ms before lock is reattained. In the invent that the switch on the input is between signals at

different datarates — for example from a 270 Mbps signal to a 1.485 Gbps input, then the lock procedure is

much more complex, and the lock time will be significantly longer. In either case, the IP that is processing the

received signal will need to reestablish the proper framing of the words.

SDI OUTPUT INTERFACING

The serial loopthrough outputs provide low-skew complementary or differential signals. The output buffer is a

current mode design, and as such has a high impedance output. To drive a 75Ω transmission line, a 75Ω resistor

from each of the output pins to V

DD2V5

should be connected. This resistor has two functions—it converts the

current output to a voltage, which is used to drive the cable, and it acts as the back termination resistor for the

transmission line. The output driver automatically adjusts its slew rate depending on the input datarate so that it

will be in compliance with SMPTE 259M, SMPTE292M or SMPTE 424M as appropriate. In addition to output

amplitude and rise/fall time specifications, the SMPTE specs require that SDI outputs meet an Output Return

Loss (ORL) specification. There are parasitic capacitances that will be present both at the output pin of the

device and on the application printed circuit board. To optimize the return loss, these must be compensated for,

usually with a series network comprising a parallel inductor and resistor. The actual values for these components

will vary from application to application, but the typical interface circuit shows values that would be a good

starting point.

Figure 7. Simplified SDI Output Circuit

JITTER MANAGEMENT

SMPTE 424M (the 3 Gbps standard) relaxed the requirements of SDI transmitters from 0.2UI to 0.3UI, which

means that the challenge of receiving these signals error free is very difficult. The parameter of importance to

determine if the DES will be able to receive the signal error free is the Jitter Tolerance. Figure 10 shows the

LMH0341 Jitter tolerance curve with a 2.97 Gbps input — any signal which has less jitter than what is on the

upper curve of Figure 10 will be able to be received by the DES. The lower line in the curve shows the SMPTE

requirement for any receiver. There is a slight dip in the level at frequencies abive about 10MHz which is an

artifact of the test equipment that was used to capture the data. Once the signal is received, the next concern as

far as jitter goes is how much of the jitter that was on the input signal will be passed through to the RXCLK

output. This is answered by the Jitter transfer characteristics. The Jitter transfer function is the ratio of the input

jitter to the output jitter, measured as a function of frequency. The specification tables show two of the

parameters related to this curve — δ is the jitter peaking and indicates what the maximum gain of the jitter is.

Ideally δ is 0, but a lower number is better. If several devices are used in a system, and the frequency at which δ

is maximum is the same for all of them, then the gains will multiply, and there is a risk that there will be

excessive jitter accumulating at that frequency. The LMH0341 has very low Jitter peaking, so this should not be a

concern. The other parameter of interest is λ which is the jitter transfer bandwidth. Jitter on the input at the

Product Folder Links: LMH0041 LMH0051 LMH0071 LMH0341