Datasheet

1005
V
DD3V3
RXIN-
RXIN+
500 PF
500 PF
8 k5
8 k5
LMH0041, LMH0051
LMH0071, LMH0341
www.ti.com SNLS272Q –APRIL 2007–REVISED APRIL 2013
LVDS OUTPUT TIMING
The DES output timing, in it's default condition, is described in LVDS Switching Characteristics. The user has the
ability to adjust the LVDS output timing to make it easier to latch into the host FPGA if desired. This is done via
register 0x28h where both the clock to data timing may be adjusted, as well as changing the RXCLK from being
a DDR clock to a clock at the rate of DDR/2
LOOP FILTER
The DES has an internal PLL which is used to recover the embedded clock from the input data. The loop filter for
this PLL has external components, and for optimum results in Serial Digital Interface applications, a capacitor
and a resistor in series should be connected between pins 26 and 27 as shown in the typical interface circuit.
DVB-ASI MODE
DVB-ASI mode is enabled when the DVB-ASI pin is brought to a high state. When the DVB-ASI mode is
enabled, an internal framer and 8b10b decoder is engaged such that the data appearing on RX0-RX3 will
represent a nibble of the decoded 8b10b data. RX4 is an Idle character detect and can be used as an enable to
allow the receiver to not write data into an external FIFO. RX4 is high if the data being presented on RX0-RX3
represents the idle character. The Least Significant Nibble of data is presented on the rising edge of RXCLK, and
the most significant on the falling edge of RXCLK.
The internal 8b10b decoder needs to receive up to 110 consecutive K28.5 characters to properly initialize and
frame the data so that the decoded 8b10b data presented at the output of the device is correct.
SDI INPUT INTERFACING
The device has two inputs, one of which is selected via a multiplexer with the RX_MUX_SEL pin. Whichever
input is selected will be routed to the clock recovery portion of the deserializer, and once it is reclocked, the
signal will be fed to the loopthrough outputs. Most SDI interfaces require an equalizer to meet performance
requirements. For HD-SDI and SD-SDI applications, the LMH0044 is an ideal equalizer to use for this. The
LMH0044 is packaged in a small compact package and the outputs can be connected directly to the RXIN inputs
of the LMH0041. The LMH0344 is pin compatible with the LMH0044 and will support 3 Gbps data, making it an
ideal choice to accompany the LMH0341.
Figure 6. Simplified SDI Input Circuit
SWITCHING SDI INPUTS
When the input to the DES is switched from one source to another, either via the internal 2:1 multiplexor on the
inputs, or via an external crosspoint switch, there are a variety of behaviors possible If the input switch is
between two signals operating at the same datarate, then in most cases, the DES will not lose lock. There will be
a small number of words with corrupted data as the PLL slews it's phase to match the new input signal. Under
some circumstances (dependent on phase difference between the inputs, temperature, etc) it is possible that the
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Product Folder Links: LMH0041 LMH0051 LMH0071 LMH0341