Datasheet

LMH0307

SNLS286I –APRIL 2008–REVISED APRIL 2013

www.ti.com

The cable driver must be enabled for the termination detection to operate. If the Termination Fault will be used to

power down the LMH0307, then periodic polling (enabling) is recommended to monitor the output termination.

For example, when a Fault condition is triggered, ENABLE can be driven low to power down the device. The

LMH0307 should be re-enabled periodically to check the status of the output termination. The LMH0307 needs to

be powered on for roughly 4 ms for Termination Fault detection to work.

SMBUS INTERFACE

The System Management Bus (SMBus) is a two-wire interface designed for the communication between various

system component chips. By accessing the control functions of the circuit via the SMBus, pin count is kept to a

minimum while allowing a maximum amount of versatility. The LMH0307 has several internal configuration

registers which may be accessed via the SMBus.

The 7-bit default address for the LMH0307 is 17h. The LSB is set to 0b for a WRITE and 1b for a READ, so the

8-bit default address for a WRITE is 2Eh and the 8-bit default address for a READ is 2Fh. The SMBus address

may be dynamically changed.

In applications where there might be several LMH0307s, the SDA, SCL, and FAULT pins can be shared. The

SCL, SDA, and FAULT pins are open drain and require external pullup resistors. Multiple LMH0307s may have

the FAULT pin wire ORed. This signal becomes active when either loss of signal is detected or any termination

faults are detected. The registers may be read in order to determine the cause. Additionally, each signal can be

masked from the FAULT pin.

TRANSFER OF DATA VIA THE SMBus

During normal operation the data on SDA must be stable during the time when SCL is High.

There are three unique states for the SMBus:

START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.

STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.

IDLE: If SCL and SDA are both High for a time exceeding t

BUF

from the last detected STOP condition or if they

are High for a total exceeding the maximum specification for t

HIGH

then the bus will transfer to the IDLE state.

SMBus TRANSACTIONS

The device supports WRITE and READ transactions. See Table 1 for register address, type (Read/Write, Read

Only), default value and function information.

WRITING A REGISTER

To write a register, the following protocol is used (see SMBus 2.0 specification).

1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.

2. The Device (Slave) drives the ACK bit (“0”).

3. The Host drives the 8-bit Register Address.

4. The Device drives an ACK bit (“0”).

5. The Host drives the 8-bit data byte.

6. The Device drives an ACK bit (“0”).

7. The Host drives a STOP condition.

The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may

now occur.

Product Folder Links: LMH0307