Datasheet

LMH0307
www.ti.com SNLS286I –APRIL 2008–REVISED APRIL 2013
Table 1. SMBus Registers (continued)
Address R/W Name Bits Field Default Description
03h R/W DIRECTION 7 HDTF0ThreshLSB 1 Least Significant Bit for HDTF0Thresh
detection threshold. Combines with
HDTF0Thresh bits in register 04h.
6 SDTF0ThreshLSB 1 Least Significant Bit for SDTF0Thresh
detection threshold. Combines with
SDTF0Thresh bits in register 05h.
5 RSVD 0 Reserved as 0. Always write 0 to this bit.
4 DTF1N 0 Direction of TF1N that affects FAULT pin
(when not masked).
0: TF1N=1 will cause FAULT to be 0 (when
the condition is not masked off).
1: TF1N=0 will cause FAULT to be 0 (when
the condition is not masked off).
3 DTF1P 0 Direction of TF1P that affects FAULT pin
(when not masked).
0: TF1P=1 will cause FAULT to be 0 (when
the condition is not masked off).
1: TF1P=0 will cause FAULT to be 0 (when
the condition is not masked off).
2 DTF0N 0 Direction of TF0N that affects FAULT pin
(when not masked).
0: TF0N=1 will cause FAULT to be 0 (when
the condition is not masked off).
1: TF0N=0 will cause FAULT to be 0 (when
the condition is not masked off).
1 DTF0P 0 Direction of TF0P that affects FAULT pin
(when not masked).
0: TF0P=1 will cause FAULT to be 0 (when
the condition is not masked off).
1: TF0P=0 will cause FAULT to be 0 (when
the condition is not masked off).
0 DLOS 0 Direction of LOS that affects FAULT pin
(when not masked).
0: LOS=0 will cause FAULT to be 0 (when
the condition is not masked off).
1: LOS=1 will cause FAULT to be 0 (when
the condition is not masked off).
04h R/W OUTPUT0 7:5 HDTF0Thresh 100 Sets the Termination Fault threshold for
SDO0, when SD is set to HD rates (0).
Combines with HDTF0ThreshLSB in
register 03h (default for combined value is
1001).
4:0 AMP0 10000 SDO0 output amplitude in roughly 5 mV
steps.
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