Datasheet
LMH0307
SNLS286I –APRIL 2008–REVISED APRIL 2013
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Table 1. SMBus Registers
Address R/W Name Bits Field Default Description
00h R/W ID 7:1 DEVID 0010111 Device ID. Writing this register will force the
RSTO pin high. Further accesses to the
device must use this 7-bit address.
0 RSVD 0 Reserved as 0. Always write 0 to this bit.
01h R STATUS 7:5 RSVD 000 Reserved.
4 TF1N 0 Termination Fault for SDI1.
0: No Termination Fault Detected.
1: Termination Fault Detected.
3 TF1P 0 Termination Fault for SDI1.
0: No Termination Fault Detected.
1: Termination Fault Detected.
2 TF0N 0 Termination Fault for SDI0.
0: No Termination Fault Detected.
1: Termination Fault Detected.
1 TF0P 0 Termination Fault for SDI0.
0: No Termination Fault Detected.
1: Termination Fault Detected.
0 LOS 0 Loss Of Signal (LOS) detect at input.
0: No Signal Detected.
1: Signal Detected.
02h R/W MASK 7 SD 0 SD Rate select bit. If the SD/HD pin is set
to V
CC
, it overrides this bit. With the SD/HD
pin set to ground, this bit selects the output
edge rate as follows:
0: HD edge rate.
1: SD edge rate.
6 PD1 0 Power Down for SDO1 output stage. If the
ENABLE pin is set to ground, it overrides
this bit. With the ENABLE pin set to V
CC
,
PD1 functions as follows:
0: SDO1 active.
1: SDO1 powered down.
5 PD0 0 Power Down for SDO0 output stage. If the
ENABLE pin is set to ground, it overrides
this bit. With the ENABLE pin set to V
CC
,
PD0 functions as follows:
0: SDO0 active.
1: SDO0 powered down.
4 MTF1N 0 Mask TF1N from affecting FAULT pin.
0: TF1N=1 will cause FAULT to be 0.
1: TF1N=1 will not affect FAULT; the
condition is masked off.
3 MTF1P 0 Mask TF1P from affecting FAULT pin.
0: TF1P=1 will cause FAULT to be 0.
1: TF1P=1 will not affect FAULT; the
condition is masked off.
2 MTF0N 0 Mask TF0N from affecting FAULT pin.
0: TF0N=1 will cause FAULT to be 0.
1: TF0N=1 will not affect FAULT; the
condition is masked off.
1 MTF0P 0 Mask TF0P from affecting FAULT pin.
0: TF0P=1 will cause FAULT to be 0.
1: TF0P=1 will not affect FAULT; the
condition is masked off.
0 MLOS 0 Mask LOS from affecting FAULT pin.
0: LOS=0 will cause FAULT to be 0.
1: LOS=0 will not affect FAULT; the
condition is masked off.
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