Datasheet

LMH0303
SNLS285G –APRIL 2008–REVISED APRIL 2013 www.ti.com
SMBUS REGISTERS
Table 1. SMBus Registers
Address R/W Name Bits Field Default Description
00h R/W ID 7:1 DEVID 0010111 Device ID. Writing this register will force the
RSTO pin high. Further accesses to the
device must use this 7-bit address.
0 RSVD 0 Reserved as 0. Always write 0 to this bit.
01h R STATUS 7:3 RSVD 00000 Reserved.
2 TFN 0 Termination Fault for SDI.
0: No Termination Fault Detected.
1: Termination Fault Detected.
1 TFP 0 Termination Fault for SDI.
0: No Termination Fault Detected.
1: Termination Fault Detected.
0 LOS 0 Loss Of Signal (LOS) detect at input.
0: No Signal Detected.
1: Signal Detected.
02h R/W MASK 7 SD 0 SD Rate select bit. If the SD/HD pin is set to
V
CC
, it overrides this bit. With the SD/HD pin
set to ground, this bit selects the output edge
rate as follows:
0: HD edge rate.
1: SD edge rate.
6 RSVD 0 Reserved as 0. Always write 0 to this bit.
5 PD 0 Power Down for SDO output stage. If the
ENABLE pin is set to ground, it overrides this
bit. With the ENABLE pin set to V
CC
, PD
functions as follows:
0: SDO active.
1: SDO powered down.
4:3 RSVD 00 Reserved as 00. Always write 00 to these bits.
2 MTFN 0 Mask TFN from affecting FAULT pin.
0: TFN=1 will cause FAULT to be 0.
1: TFN=1 will not affect FAULT; the condition
is masked off.
1 MTFP 0 Mask TFP from affecting FAULT pin.
0: TFP=1 will cause FAULT to be 0.
1: TFP=1 will not affect FAULT; the condition
is masked off.
0 MLOS 0 Mask LOS from affecting FAULT pin.
0: LOS=0 will cause FAULT to be 0.
1: LOS=0 will not affect FAULT; the condition
is masked off.
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