Datasheet

SDI 143 MBPS DATANO DATA
T
2
270 MBPS DATA 1485 MBPS DATA 270 MBPS DATA
T
1
T
ACQ
T
2
T
2
SDI 270 MBPS DATANO DATA
Lock
Detect
SD/HD
T
2
NO DATA 1485 MBPS DATA NO DATA
T
2
Lock
Detect
SD/HD
T
ACQ
= Acquisition Time, defined in the AC Electrical Characteristics Table
T
1
= Time from Lock Detect assertion or deassertion until SD/HD output is valid, typically 37 ns (one 27 MHz clock period)
T
2
= Time from SDI input change until Lock Detect de-assertion, 1 ms maximum. SD/HD output is not valid during this time.
T
1
T
1
T
ACQ
T
1
T
ACQ
T
ACQ
T
1
T
1
T
ACQ
T
1
T
1
T
ACQ
T
1
LMH0046
www.ti.com SNLS222F –APRIL 2006–REVISED APRIL 2013
Figure 6. SDI, Lock Detect, and SD/HD Timing
SCO_EN
Input SCO_EN enables the SCO/SDO2 differential output to function either as a serial data-rate clock or second
serial data output. SCO/SDO2 functions as a serial data-rate clock when SCO_EN is high. This pin has an
internal pull-down device. The default state (low) enables the SCO/SDO2 output as a second serial data output.
CRYSTAL OR EXTERNAL CLOCK REFERENCE
The LMH0046 uses a 27 MHz crystal or external clock signal as a timing reference input. A 27 MHz parallel
resonant crystal and load network may be connected to the XTAL IN/EXT CLK and XTAL OUT pins.
Alternatively, a 27 MHz LVCMOS compatible clock signal may be input to XTAL IN/EXT CLK. Parameters for a
suitable crystal are given in Table 4.
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