Datasheet

TXCLK
80%
20%
t
CIT
80%
20%
t
CIT
TXCLK
TXn
Setup
Hold
t
CIL
, t
CIH
t
CIP
/2
t
STC
t
HTC
+100 mV
-100 mV
0V
0V
LMH0040, LMH0050
LMH0070, LMH0340
SNLS271I –APRIL 2007–REVISED APRIL 2013 www.ti.com
LVDS Switching Characteristics
Over supply and Operating Temperature ranges unless otherwise specified.
(1)
Symbol Parameter Condition Min Typ Max Units
t
CIP
TxCLKIN Period See Figure 2 3.2 2T 37 ns
t
CIT
TxCLKIN Transition Time See Figure 3 0.5 1.0 3.0 ns
t
CIH
TxCLKIN IN High Time See Figure 2 0.7T T 1.3T ns
t
CIL
TxCLKIN IN Low Time See Figure 2 0.7T T 1.3T ns
t
XIT
TxIN Transition Time 0.15 3 ns
t
STC
TxIN Setup to TxCLKIN See Figure 2
(2)
-550 ps
t
HTC
TxIN Hold to TxCLKIN 900 ps
(1) Typical Parameters measured at V
DD3V3
=3.3V, V
DD2V5
=2.5V, T
A
=25°C. They are for reference purposes and are not production tested.
(2) Parameter uses default settings in registers: 0x24'h and 0x30'h.
Figure 2. LVDS Input Timing Diagram
Figure 3. Transmit Clock Transition Times
SMBus Input Electrical Characteristics
Over supply and Operating Temperature ranges unless otherwise specified.
(1)
Symbol Parameter Condition Min Typ Max Units
V
SIL
Data, Clock Input Low Voltage 0.8 V
V
SIH
Data, Clock Input High Voltage 2 V
SDD
V
I
SPULLUP
Current through pull-up resistor or
(2)
4 mA
current source
V
SDD
Nominal Bus Voltage 2.375 3.6 V
I
SLEAKB
Input Leakage per bus segment
(2)
−200 200 μA
I
SLEAKP
Input Leakage per pin −10 10 μA
C
SI
Capacitance for SMBdata and SMBclk
(2) (3)
10 pF
R
STERM
Termination Resistance V
SDD3V3
(4) (3) (2)
1000 Ω
(1) Typical Parameters measured at V
DD3V3
=3.3V, V
DD2V5
=2.5V, T
A
=25°C. They are for reference purposes and are not production tested.
(2) Recommended value—Parameter is not tested.
(3) Recommended maximum capacitance load per bus segment is 400 pF.
(4) Maximum termination voltage should be identical to the device supply voltage.
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