Datasheet

LMH0040, LMH0050
LMH0070, LMH0340
www.ti.com SNLS271I –APRIL 2007–REVISED APRIL 2013
PIN DESCRIPTIONS
Pin Name Type Description
LVDS Input Interface
TX[4:0]+ Input, LVDS LVDS Data Input Pins
TX[4:0]- Five channel wide DDR interface. Internal 100Ω termination.
TXCLK+ Input, LVDS LVDS Clock Input Pins
TXCLK- DDR Interface. Internal 100Ω termination.
Serial Output Interface
TXOUT+ Output, CML Serial Digital Interface Output Pin
Non-Inverting Output
TXOUT- Output, CML Serial Digital Interface Output Pin
Inverting Output
SMBus Interface
SDA I/O, LVCMOS SMBus Data I/O Pin
SCK Input, LVCMOS SMBus Clock Input Pin
SMB_CS Input, LVCMOS SMBus Chip Select Input Pin
Device is selected when High.
Control and Configuration Pins
RESET Input, LVCMOS Reset Input Pin
H = normal mode
L = device in RESET
LOCK Output, LVCMOS PLL LOCK Status Output
H = unlock condition
L = Device is Locked
DVB_ASI Input, LVCMOS DVB_ASI Select Input
H = DVB_ASI Mode enabled
L = Normal Mode enabled
GPIO[2:0] I/O, LVCMOS General Purpose Input / Output
Software configurable I/O pins.
RSVD_H Input, LVCMOS Configuration Input – Must tie High
Pull High via 5 kΩ resistor to V
DD3V3
Analog Inputs
R
SET
Input, analog Serial Output Amplitude Control
Resistor connected from this pin to ground to set the signal amplitude. Nominally
8.06kΩ for 800mV output (SMPTE).
LF_CP Input, analog Loop Filter Connection
LF_REF Input, analog Loop Filter Reference
DNC Do Not Connect – Leave Open
Power Supply and Ground
V
DD3V3
Power 3.3V Power Supply connection
V
DDPLL
Power 3.3V PLL Power Supply connection
V
DD2V5
Power 2.5V Power Supply connection
GND Ground Ground connection – The DAP (large center pad) is the primary GND connection for
the device and must be connected to Ground along with the GND pins.
Table 1. Feature Table
SMPTE 424M SMPTE 292M SMPTE 259M DVB-ASI SMPTE compliant
Device
Support (3G) Support (HD) Support (SD) Support Cable Driver
LMH0340 X X X X X
LMH0040 X X X X
LMH0070 X X X
LMH0050 X X X
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Product Folder Links: LMH0040 LMH0050 LMH0070 LMH0340