Datasheet
FPGA Host
LMH0050
+
-
+
-
+
-
+
-
+
-
+
-
TX4
TX3
TX2
TX1
TX0
TXCLK
SDA
SCK
SMB_CS
100ÖTWP
9.1 kÖ
500Ö
RSET
LF_REF
LF_CP
TXOUT+
TXOUT-
LVDS Outputs
LVCMOS GPIO
SMBus Interface
GPIO_0
GPIO_1
GPIO_2
V
DD 2V5
V
DD 3V3
3.3V 2.5V
V
DDPLL
3.3V
5 k:
GND
RSVD_H
1,36
7,15,18,
25,35
2,5
DAP,8,9,10,12,13,
21,22,23,24,29
3
4
11
14
16
17
26
27
28
34
33
32
38
37
40
39
42
41
44
43
46
45
48
47
1 kÖ
22 PF
3.3V
0.1 PF
3.3V
3.3V
1 kÖ
All Bypass CAPS
not shown
DVB_ASI
LOCK
RESET
6
31
30
DNC
19, 20
LMH0040, LMH0050
LMH0070, LMH0340
www.ti.com
SNLS271I –APRIL 2007–REVISED APRIL 2013
Figure 15. Typical LMH0050 CML Application Circuit
SERIAL JITTER OPTIMIZATION
The SER is capable of very low jitter operation, however it is dependent on the TXCLK provided by the host in
order to operate, and depending on the quality of the TXCLK provided, the SER output jitter may not be as low
as it could be.
The SER includes circuitry to filter out any TXCLK jitter at frequencies above 1MHz (see Figure 16), however, for
frequencies below 100 kHz, any jitter that is in the TXCLK is passed directly through to the serialized output.
In most cases, passing the TXCLK through the FPGA will add high frequency noise to the signal, which will be
filtered out by the SER, resulting in a clean output, however for better jitter performance, it is best to minimize the
noise that is on the TXCLK that is provided to the SER. This can be done by careful routing of the CLK signals,
both within the FPGA and on the board.
Very clean clocks can be derived from video reference signals through the use of the LMH1981 Sync Separator
and the LMH1982 Clock Generator products from Texas Instruments. These products allow low jitter video
frequency clocks to be generated either independently, or phase locked to a video reference signal.
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Product Folder Links: LMH0040 LMH0050 LMH0070 LMH0340