Datasheet
FPGA Host
LMH0340
+
-
+
-
+
-
+
-
+
-
+
-
TX4
TX3
TX2
TX1
TX0
TXCLK
SDA
SCK
SMB_CS
75Ö
75Ö
75Ö
75Ö
6.8 nH
SDI Output
8.06 kÖ
500Ö
RSET
LF_REF
LF_CP
TXOUT+
TXOUT-
LVDS Outputs
LVCMOS GPIO
SMBus Interface
GPIO_0
GPIO_1
GPIO_2
V
DD 2V5
V
DD 3V3
3.3V 2.5V
2.5V
4.7 PF
V
DDPLL
3.3V
5 k:
GND
RSVD_H
1,36
7,15,18,
25,35
2,5
DAP,8,9,10,12,13,
21,22,23,24,29
3
4
6
11
14
16
17
26
27
28
34
33
32
38
37
40
39
42
41
44
43
46
45
48
47
1 kÖ
4.7 PF
22 PF
3.3V
0.1 PF
3.3V
3.3V
1 kÖ
All Bypass
CAPS not
shown
DVB_ASI
LOCK
RESET
31
30
DNC
19, 20
LMH0040, LMH0050
LMH0070, LMH0340
www.ti.com
SNLS271I –APRIL 2007–REVISED APRIL 2013
The PLL loop filter is external for the SER. A capacitor is connected in series to a resistor between the LF_CP
and LF_REF pins. Typical values are 500 Ω and 0.1 µF.
There are several configuration pins that requiring setting to the proper level. The RSVD_H pins should be pulled
High to the 3.3V rail with a 5 kΩ resistor. Depending upon the application the DVB_ASI pin may be tied off or
driven.
There are three supply connections (see PLL FILTER / BYPASS and for recommendations). The two main
supplies are the 3.3V rail and the 2.5V rail. There is also a 3.3V connection for the PLL circuitry.
There are multiple Ground connections for the device. The main ground connection for the SER is through the
large center DAP pad. This must be connected to ground for proper device operation. In addition, multiple other
inputs are required to be connected to ground as show in Figure 14 and listed in .
Figure 14. Typical SMPTE Application Circuit
TYPICAL LMH0050 CML APPLICATIONS CIRCUIT
A typical application circuit for the LMH0050 is shown in Figure 15.
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Product Folder Links: LMH0040 LMH0050 LMH0070 LMH0340