Datasheet

LMH0031
SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified
(1)
.
Symbol Parameter Conditions Reference Min Typ Max Units
Serial Video Data Inputs
SMPTE 259M, Level C 270
SMPTE 259M, Level D 360
BR
SDI
Serial Input Data Rate SMPTE 344M 540 M
BPS
SMPTE 292M 1,483
SDI, SDI
SMPTE 292M 1,485
20%–80%, SMPTE 259M
0.4 1.0 1.5 ns
Data Rates
t
r
, t
f
Rise Time, Fall Time
20%–80%, SMPTE 292M
270 ps
Data Rates
Parallel Video Data Outputs
SMPTE 259M, 270M
BPS
27.0
SMPTE 267M, 360M
BPS
36.0
Video Output Clock
f
VCLK
SMPTE 344M, 540M
BPS
V
CLK
54.0 MHz
Frequency
SMPTE 292M, 1,483M
BPS
74.176
SMPTE 292M, 1,485M
BPS
74.25
Propagation Delay, Video V
CLK
to DV
N
t
pd
50%–50% 0.5 2.0 ns
Clock to Video Data Valid Timing Diagram
DC
V
Duty Cycle, Video Clock V
CLK
50±5 %
27MHz 2.0
36MHz 1.4
Video Data Output Clock
t
JIT
V
CLK
ns
P-P
Jitter
54MHz 1.0
74.25MHz 0.5
Parallel Ancillary / Control Data Inputs, Multi-function Parallel Bus Inputs
Ancillary / Control Data Clock
f
ACLK
V
CLK
MHz
Frequency
A
CLK
Duty Cycle, Ancillary Data
DC
A
ANC Data clock
(2)
45 50 55 %
Clock
t
r
, t
f
Output Rise Time, Fall Time 10%–90% 1.0 1.5 3.0
Setup Time, AD
N
to A
CLK
or
t
S
IO
N
, AD
N
, A
CLK
3.0 1.5
IO
N
to A
CLK
Rising Edge ns
Control Data Input or I/O Bus
Timing Diagram
Input
Hold Time, Rising Edge A
CLK
t
H
3.0 1.5
to AD
N
or A
CLK
to IO
N
Parallel Ancillary / Control Data Outputs
Propagation Delay, Clock to
t
pd
8.5
Control Data
A
CLK
to AD
N
50%–50% ns
Timing Diagram
Propagation Delay, Clock to
t
pd
11.5
Ancillary Data
Multi-function Parallel I/O Bus
IO0–IO7
t
r
, t
f
Rise Time, Fall Time 10%–90% 1.0 1.5 3.0 ns
Timing Diagram
PLL/CDR, Format Detect
SD Rates
(3)
0.32 1.0
t
LOCK
Lock Detect Time
HD Rates
(3)
0.26 1.0 ms
t
FORMAT
Format Detect Time All Rates 20
(1) Typical values are stated for V
DDIO
= V
DDSI
= +3.3V, V
DDD
= V
DDPLL
= +2.5V and T
A
= +25°C.
(2) When used to clock control data into or from the LMH0031, the duty cycle restriction does not apply.
(3) Measured from rising-edge of first SDI cycle until Lock Detect bit goes high (true). Lock time includes CDR phase acquisition time plus
PLL lock time.
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