Datasheet
LMH0031
www.ti.com
SNLS218A –JANUARY 2006–REVISED APRIL 2013
Table 4. Video Raster Format Parameters
Format
Frame Active
Code Format Spec.
(1)
Lines Active Lines Samples
Rate Samples
[4,3,2,1,0]
00001 SDTV, 54 RP 174 60I 525 507/487* 3432 2880
00010 SDTV, 36 SMPTE 267 60I 525 507/487* 2288 1920
00011 SDTV, 27 SMPTE 125 60I 525 507/487* 1716 1440
01001 SDTV, 54 ITU-R BT 601.5 50I 625 577 3456 2880
01010 SDTV, 36 ITU-R BT 601.5 50I 625 577 2304 1920
01011 SDTV, 27 ITU-R BT 601.5 50I 625 577 1728 1440
10001 HDTV, 74.25 SMPTE 260 30I 1125 1035 2200 1920
10010 HDTV, 74.25 SMPTE 274 30I 1125 1080 2200 1920
10011 HDTV, 74.25 SMPTE 274 30P 1125 1080 2200 1920
11001 HDTV, 74.25 SMPTE 274 25I 1125 1080 2640 1920
11010 HDTV, 74.25 SMPTE 274 25P 1125 1080 2640 1920
11100 HDTV, 74.25 SMPTE 295 25I 1250 1080 2376 1920
11101 HDTV, 74.25 SMPTE 274 24P 1125 1080 2750 1920
10100 HDTV, 74.25 SMPTE 296 (1, 2) 60P 750 720 1650 1280
(1) Spec. is ensured by design.
The HD Only bit when set to a logic-1 locks the LMH0031 into the high definition data range and frequency. In
systems designed to handle only high definition signals, enabling HD Only reduces the time required for the
LMH0031 to establish frequency lock and determine the HD format being processed.
The SD Only bit when set to a logic-1 locks the LMH0031 into the standard definition data ranges and
frequencies. In systems designed to handle only standard definition signals, enabling SD Only reduces the time
required for the LMH0031 to establish frequency lock and determine the format being processed. When SD Only
and HD Only are set to logic-0, the device operates in SD/HD mode.
The Framing Mode bit in the Format 0 register and Framing Enable in the Video Info 0 register combine with
Framing Enable to control the manner in which the LMH0031 aligns framing. When Framing Mode and
Framing Enable are both reset, the LMH0031 aligns on the first valid TRS character. If another TRS occurs that
is not on a word boundary, the NSP bit is set until the next TRS that is on a word boundary occurs. When
Framing Mode is set to a logic-1, the LMH0031 operates similarly to the CLC011 when NSP is tied to FE. An
alternative configuration that operates identically can be achieved with the LMH0031 by mapping NSP as an
output and Framing Enable as an input on the Multifunction I/O bus and externally connecting them. In this case
Framing Mode should be reset to a logic-0. When Framing Mode is reset and Framing Enable is set, the
LMH0031 realigns on every valid TRS. The initial state of Framing Mode is set following a reset or at power-on.
FORMAT 1 (Address 0Ch)
The LMH0031 automatically determines the format of the incoming serial data. The result of this operation is
stored in the FORMAT 1 register. The Format[4:0] bits identify which of the many possible video data standards
that the LMH0031 can process is being received. These format codes follow the same arrangement as for the
Format Set[4:0] bits. These formats and codes are given in Table 4. Bit Format[4] when set indicates that HD
data is being processed. When reset, SD data is indicated. Format[3] when set indicates that PAL data is being
processed. When reset NTSC data is being processed. Format[2:0] correspond with one of the sub-standards
given in the table. Note that the LMH0031 does not distinguish or log the data rate differences between HD data
at 74.25Mhz and 74.25MHz/1.001.
The H, V, and F bits correspond to input TRS data bits 6, 7 and 8, respectively. The meaning and function of this
data is the same for both standard definition (SMPTE 125M) and high definition (SMPTE 292M luminance and
colour difference) video data. Polarity is logic-1 equals HIGH-true. These bits are registered for the duration of
the applicable field.
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