Datasheet
LMH0031
SNLS218A –JANUARY 2006–REVISED APRIL 2013
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Table 3. Control Register Addresses
Address
Register Name
Hexadecimal
EDH 0 01
EDH 1 02
EDH 2 03
ANC 0 04
ANC 1 05
ANC 2 06
ANC 3 07
ANC 4 08
ANC 5 17
ANC 6 18
FORMAT 0 0B
FORMAT 1 0C
TEST 0 0D
VIDEO INFO 0 0E
I/O PIN 0 CONFIG 0F
I/O PIN 1 CONFIG 10
I/O PIN 2 CONFIG 11
I/O PIN 3 CONFIG 12
I/O PIN 4 CONFIG 13
I/O PIN 5 CONFIG 14
I/O PIN 6 CONFIG 15
I/O PIN 7 CONFIG 16
VIDEO CONTROL 0 55
VIDEO CONTROL 1 56
REFERENCE CLOCK 67
EDH 0 (register 01h)
The EDH Full-Field flags F/F UES, F/F IDA, F/F IDH, F/F EDA andF/F EDH are defined in SMPTE RP 165. The
flags are updated automatically when the EDH function is enabled and data is being received.
The EDH ENABLE bit, when set, enables operation of the EDH generator function during SD operation. The
default condition of this bit is set (ON).
The EDH FORCE bit, when set, causes updated EDH packets to be inserted in the parallel output data
regardless of the previous condition of EDH checkwords and flags in the input serial data. This function may be
used in situations where video content has been edited thus making the previous EDH information invalid. The
default condition of this bit is reset (OFF).
The CRC ERROR bit indicates that errors in either the EDH checksums (SD) or CRC checkwords (HD) were
detected in the serial input data. This bit is a combined function which indicates the presence of either EDH
errors during SD operation or CRC errors during HD operation.
EDH 1 (register 02h)
The EDH Active Picture flags A/P UES, A/P IDA, A/P IDH, A/P EDA andA/P EDH are defined in SMPTE RP
165. The flags are updated automatically when the EDH function is enabled and data is being received.
Specific types of CRC errors in incoming HD serial data are reported in the CRC ERROR LUMA and CRC
ERROR CHROMA bits.
The CRC REPLACE bit, when set, causes the CRCs in the incoming data to be replaced with CRCs calculated
by the LMH0031. The bit is normally reset (OFF).
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