Datasheet

LMH0030
www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013
AC ELECTRICAL CHARACTERISTICS (continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified
(1)
.
Symbol Parameter Conditions Reference Min Typ Max Units
t
j
Serial Output Jitter, 270 M
bps
,
(2) (5) (6) (7)
SDO, SDO
270 350 ps
P-P
Intrinsic
t
j
Serial Output Jitter, 1,485 M
bps
,
(3) (5) (6) (7)
SDO, SDO
85 125 ps
P-P
Intrinsic
t
LOCK
Lock Time See
(2) (8) (9)
(SD Rates) 15 ms
t
LOCK
Lock Time See
(3) (8)(9)
(HD Rates) 15 ms
t
S
Setup Time, Video Data Timing Diagram,
(4)
DV
N
to V
CLK
1.5 2.0 ns
t
H
Hold Time, Video Data Timing Diagram,
(4)
V
CLK
to DV
N
1.5 2.0 ns
t
S
Setup Time, Anc. Data Timing Diagram,
(4)
AD
N
to A
CLK
1.5 2.0 ns
Port
t
H
Hold Time, Anc. Data Port Timing Diagram,
(4)
A
CLK
to AD
N
1.5 2.0 ns
(5) Intrinsic timing jitter is measured in accordance with SMPTE RP 184-1996, SMPTE RP 192-1996 and the applicable serial data
transmission standard, SMPTE 259M-1997 or SMPTE 292M-1998. A color bar test pattern is used. The value of f
SCLK
is 270 MHz or
360 MHz for SMPTE 259M, 540MHz for SMPTE 344M, or 1485 MHz for SMPTE 292M serial data rates. See Timing Jitter Bandpass
section.
(6) Intrinsic jitter is defined in accordance with SMPTE RP 184-1996 as: jitter at an equipment output in the absence of input jitter. As
applied to this device, the input port is V
CLK
and the output port is SDO or SDO.
(7) Specification is ensured by characterization.
(8) Measured from rising-edge of first DV
CLK
cycle until Lock Detect output goes high (true). Lock time includes format detection time plus
PLL lock time.
(9) Average value measured between rising edges computed over at least one video field.
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