Datasheet

LMH0030
www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013
Table 6. I/O Configuration Register Addresses for Control Register Functions
Bit Address Pin # SEL [n]
Power-On
Register Bit I/P or O/P
Status
[5] [4] [3] [2] [1] [0]
reserved 0 0 0 0 0 0
FF Flag Error 0 0 0 0 0 1 Output
AP Flag Error 0 0 0 0 1 0 Output
ANC Flag 0 0 0 0 1 1 Output
Error
CRC Error 0 0 0 1 0 0 Output I/O Port Bit 5
(SD/HD)
Addresses x05h through x0Ch are reserved.
SAV 0 0 1 1 0 1 Output
EAV 0 0 1 1 1 0 Output
NSP 0 0 1 1 1 1 Output
F 0 1 0 0 1 0 Output I/O Port Bit 0
V 0 1 0 0 1 1 Output I/O Port Bit 1
H 0 1 0 1 0 0 Output I/O Port Bit 2
Format[0] 0 1 0 1 0 1 Output
Format[1] 0 1 0 1 1 0 Output
Format[2] 0 1 0 1 1 1 Output
Format[3] 0 1 1 0 0 0 Output
Format[4] 0 1 1 0 0 1 Output I/O Port Bit 3
(SD/HD)
FIFO Full 0 1 1 0 1 0 Output
FIFO Empty 0 1 1 0 1 1 Output
Lock Detect 0 1 1 1 0 0 Output I/O Port Bit 4
Pass/Fail 0 1 1 1 0 1 Output I/O Port Bit 6
FIFO Overrun 0 1 1 1 1 0 Output
ANC Chksum 0 1 1 1 1 1 Output
Error
EDH Force 1 0 0 0 0 0 Input
Test Pattern 1 0 0 0 0 1 Input
Select[0]
Test Pattern 1 0 0 0 1 0 Input
Select[1]
Test Pattern 1 0 0 0 1 1 Input
Select[2]
Test Pattern 1 0 0 1 0 0 Input
Select[3]
Test Pattern 1 0 0 1 0 1 Input
Select[4]
Test Pattern 1 0 0 1 1 0 Input
Select[5]
EDH Enable 1 0 0 1 1 1 Input
TPG Enable 1 0 1 0 0 0 Input I/O Port Bit 7
reserved 1 0 1 0 0 1
Chksum 1 0 1 0 1 0 Input
Attach In
reserved 1 0 1 0 1 1
VPG Filter 1 0 1 1 0 0 Input
Enable
Dither Enable 1 0 1 1 0 1 Input
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