Datasheet

LMH0030
SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com
When ANC MASK[7:0] or ANC MASK[15:8] is set to FFh, packets with any DID, SDID or DBN can be loaded
into the FIFO. When any bit or bits of ANC MASK[7:0] or ANC MASK[15:8] are set to a logic-1, the
corresponding bit or bits of ANC ID[7:0] or ANC ID[15:8], respectively are a don't-care when matching IDs of
incoming packets. When ANC MASK[7:0] or ANC MASK[15:8] is set to 00h, the DID, SDID or DBN of incoming
packets must match exactly, bit-for-bit, the setting of ANC ID[7:0] or ANC ID[15:8] in the control register for the
packets to be loaded into the FIFO. The initial value of ANC MASK[7:0] and ANC MASK[15:8] is FFh. The initial
value of ANC ID[7:0] and ANC ID[15:8] is 00h.
Bits 7 through 0 of Register ANC 1, ANC ID[7:0], and Register ANC3, ANC MASK[7:0], affect DID[7:0]. BIts 7
through 0 of Register ANC2, ANC ID[15:8], and Register ANC 4, ANC MASK[15:8], affect SDID[7:0] or
DBN[7:0].
ANC REGISTER 5 (Address 17h)
The FIFO INSERT ENABLE bit enables insertion of ancillary data stored in the FIFO into the serial data stream.
Data insertion is enabled when this bit is set to a logic-1. This bit can be used to delay automatic insertion of data
into the serial data stream.
Setting the FIFO FLUSH STAT bit to a logic-1 flushes the FIFO. Data may not be loaded into the FIFO during
FIFO FLUSH STAT execution. Similarly, FIFO FLUSH STAT may not be set when data is being input to the
FIFO. FIFO FLUSH STAT is automatically reset after this operation is complete. Execution of these FIFO
operations requires toggling of ACLK.
ANC REGISTER 6 (Addresses 18h)
The ANC PARITY MASK bit when set disables parity checking for the DATA ID (DID) and SECONDARY DATA
ID (SDID) or Data Block Number (DBN) in the ANC data packet. When reset, parity checking is enabled, and, if a
parity error occurs, the packet will not be loaded.
The VANC bit in the control registers, when set to a logic-1, enables insertion of ancillary data during the vertical
blanking interval.
SWITCH POINT REGISTERS 0 THROUGH 3 (Addresses 09h, 0Ah, 19h and 1Ah)
The Line[10:0] and Protect[4:0] bits define the vertical switching point line and number of protected lines
following the switching point line for fields 0 and 1 (or fields 1 and 2 as these are sometimes referred to) of high-
defination formats. The vertical switching point for component digital standard definition formats is defined in
SMPTE RP 168-1993. The vertical switching point for high-definition formats has the same basic definition.
However, since the vertical switching point lines are not necessarily standardized among the various high-
definition rasters, these registers provide a convenient means whereby the vertical switching point line and
subsequent protected lines may be specified by the user. The Switch Point registers do not operate for standard
definition formats.
The Line[10:0] bits of registers Switch Point 0 and 1 may be loaded with a line number ranging from 0 to 1023
which then specifies the switching point line for Field 0. The Protect[4:0] bits of register Switch Point 1
determine the number of lines from 0 to 15 after the vertical switching point line in which ancillary data may not
be inserted. LINE(0) is the LSB and LINE(10) is the MSB for the Line[10:0] bits. Similar ordering holds for the
Protect[4:0] bits.
The Line[10:0] and Protect[4:0] bits of registers Switch Point 2 and 3 perform the same function as explained
above for the vertical switching point line for Field 1.
FORMAT REGISTERS 0 (Addresses 0Bh)
The LMH0030 may be set to process a single video format by writing the appropriate data into the FORMAT 0
register. The Format Set[4:0] bits confine the LMH0030 to recognize and process only one of the fourteen
specified types of standard or high definition formats. When the LMH0030 is set to process a single format, it will
not recognize and therefore will not process other formats that it is capable of recognizing. The Format Set[4:0]
bits may not be used to confine device operation to a range of standards. For normal operating situations, it is
recommended that the LMH0030 be operated in automatic format detection mode, i.e. that the Format 0 register
be set to 00h.
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