Datasheet

LMH0030
www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013
The Pass/Fail bit in the TEST 0 control register indicates the test status. If no errors have been detected, this bit
will be set to logic-1 approximately 2 field intervals after TPG Enable is set. If errors have been detected in the
internal circuitry of the LMH0030, Pass/Fail will remain reset to a logic-0. The TPG or BIST is halted by resetting
TPG Enable. The serial output data is present at the SDO outputs during TPG or BIST operation.
CAUTION
When attempting to use the TPG or BIST immediately after applying power or resetting
the device, the TPG defaults to the 270 Mbps SD rate and expects a V
CLK
clock
frequency of 27MHz as input. This is because the code for the test pattern in the TEST
0 register is set to 00h (525 line, 30 frame, 27MHz, NTSC 4x3 reference black).
Attempting to apply a V
CLK
frequency higher than the device expects, according to the
setting in the TEST 0 register, may result in the PLL locking up while attempting to
slew to its maximum possible frequency. This situation is not recoverable by the use of
the device RESET input. To recover from this condition, power must be removed and
re-applied to the device. Proper conditioning of the V
CLK
input, which does not have an
internal pull down device, is mandatory to prevent admission of noise or unwanted
signals at any time, especially during power-up or reset sequences. It is strongly
recommended that V
CLK
not be applied until device initialization and configuration is
completed.
Example: Enable the TPG Mode to use the NTSC 270 Mbps color bars as the BIST and TPG pattern. Enable
TPG operation using the I/O port.
1. Set ANC/CTRL to a logic-low.
2. Set RD/WR to a logic-low.
3. Present 00Dh to AD[9:0] as the TEST 0 register address.
4. Toggle ACLK.
5. Present 303h to AD[9:0] as the register data (525 line, 30 frame, 27MHz, NTSC 4x3, color bars (SMPTE
125M)).
6. Toggle ACLK.
7. Set TPG ENABLE (I/O Port, bit 7) to a logic-high.
8. Toggle ACLK.
9. The PASS/FAIL indicator (I/O Port, bit 6) is monitored for the result of the test. Alternatively, the TEST 0
register may be read. Bit 7 is the Pass/Fail indicator bit.
CONFIGURATION AND CONTROL REGISTERS
The configuration and control registers store data which configures the operational modes of the LMH0030 or
which result from its operation. Many of these registers can be mapped to the multi-function I/O bus to make
them available as external I/O functions. These functions and initial values are summarized in Table 1 and
detailed in Table 2. The power-on default condition for the multi-function I/O port is indicated in Table 1 and
detailed in Table 6.
Table 1. Configuration and Control Data Register Summary
Assignable to
Register Function Bits Read or Write Initial Condition
(1)
Notes
I/O Bus as
EDH Error (SD) 1 R Output See
(1)
Full-Field Flags 5 R Reset No
Active Picture Flags 5 R Reset No
ANC Flags 5 R Reset No
EDH Force 1 R/W OFF Input
EDH Enable 1 R/W ON Input
F/F Flag Error 1 R Reset Output
(1) ON = logic-1, OFF = logic-0 (positive logic).
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