Datasheet

LMH0030
SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com
CAUTION
This output buffer is not designed or specified for driving 50Ω or other impedance
loads.
NOTE
The SMPTE return loss specification is highly dependent on board design and can be
challenging to meet with the LMH0030's integrated cable driver. In order to meet the
SMPTE return loss specification, it is recommended to use an external cable driver such
as the LMH0002 HD/SD SDI cable driver on the output of the LMH0030.
POWER SUPPLIES, POWER-ON-RESET AND RESET INPUT
The LMH0030 requires two power supplies, 2.5V for the core logic functions and 3.3V for the I/O functions. The
supplies must be applied to the device in proper sequence. The 3.3V supply must be applied prior to or
coincident with the 2.5V supply. Application of the 2.5V supply must not precede the 3.3V supply. It is
recommended that the 3.3V supply be configured or designed so as to control application of the 2.5V supply in
order to satisfy this sequencing requirement.
The LMH0030 has an automatic, power-on-reset circuit. Reset initializes the device and clears TRS detection
circuitry, all latches, registers, counters and polynomial generators, sets the EDH/CRC characters to 00h and
disables the serial output. Table 1 lists the initial conditions of the configuration and control registers. An active-
HIGH-true, manual reset input is available at pin 64. The reset input has an internal pull-down device and may
be considered inactive when unconnected.
Important: When power is first applied to the device or following a reset, the Ancillary and Control Data Port
must be initialized to receive data. This is done by toggling ACLK three times.
TEST PATTERN GENERATOR (TPG) AND BUILT-IN SELF-TEST (BIST)
The LMH0030 includes a built-in test pattern generator (TPG). Four test pattern types are available for all data
rates, all HD and SD formats, NTSC and PAL standards, and 4x3 and 16x9 raster sizes. The test patterns are:
flat-field black, PLL pathological, equalizer (EQ) pathological and a 75%, 8-color vertical bar pattern. The
pathologicals follow the recommendations of SMPTE RP 178-1996 regarding the test data used. The color bar
pattern has optional bandwidth limiting coding in the chroma and luma data transitions between bars. The VPG
FILTER ENABLE bit in the VIDEO INFO 0 control register enables the color bar filter function. The default
condition of VPG FILTER ENABLE is OFF.
The TPG also functions as a built-in self-test (BIST) which can verify device functionality. The BIST function
performs a comprehensive go/no-go test of the device. The test may be run using any of the HD color bar test
patterns or one of two SD test patterns, either a 270 Mbps NTSC full-field color bar or a PAL PLL pathological,
as the test data pattern. Data is supplied internally in the input data register, processed through the device and
tested for errors using either the EDH system for SD or the CRC system for HD. A go/no-go indication is logged
in the Pass/Fail bit of the TEST 0 control register set. This bit may be assigned as an output on the multifunction
I/O port.
TPG and BIST operation is initiated by loading the code for the desired test pattern into the Test Pattern Select
[5:0] bits of the TEST 0 register. Table 5 gives the available test patterns and codes. (Recall also the
requirement to initialize the ancillary data port control logic by clocking ACLK at least three (3) complete cycles
before attempting to load the first register address). In the default power-on state, TPG Enable appears as bit 7
on the multi-function I/O port. The TPG is run by applying the appropriate frequency at the VCLK input for the
format and rate selected and then setting the TPG Enable input on the multi-function I/O port, or by setting the
TPG Enable bit in the TEST 0 register.
Important: If the TPG Enable input of the I/O port is in its default mapping and is not being used to enable the
TPG mode, attempting to enable TPG operation by setting bit 6 of the TEST 0 register will not cause the TPG to
operate. This is because the low logic level at the I/O port input pulldown overrides the high level being written to
the register. The result is the TPG does not run.
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