Datasheet

LMH0030
www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013
EDH/CRC SYSTEM
The LMH0030 has EDH and CRC character generation and insertion circuitry. The EDH system functions as
described in SMPTE Recommended Practice RP-165. The CRC system functions as specified in SMPTE 292M.
The EDH/CRC polynomial generators accept parallel data from the input register and generate the EDH and
CRC check words for insertion in the serial data. Incoming parallel data is checked for errors and the EDH flags
are updated automatically. EDH check words and status flags for SDTV data are generated using the polynomial
X
16
+ X
12
+ X
6
+ 1 per SMPTE RP165. EDH check words are inserted in the serial data stream at the correct
positions in the ancillary data space and formatted per SMPTE 291M. Generation and automatic insertion of the
EDH check words is controlled by EDH Force and EDH Enable bits in the control registers. After a reset, the
initial state of all EDH and CRC check characters is 00h.
The SMPTE 292M high definition video standard employs CRC (cyclic redundancy check codes) error checking
instead of EDH. The CRC consists of two 18-bit words generated using the polynomial X
18
+ X
5
+ X
4
+ 1 per
SMPTE 292M. One CRC is used for luminance and one for chrominance data. CRC data is inserted at the
required place in the video data according to SMPTE 292M. The CRCs appear in the data stream following the
EAV and line number characters.
EDH and CRC errors are reported in the EDH0, EDH1, and EDH2 register sets of the configuration and control
registers.
PHASE-LOCKED LOOP SYSTEM
The phase-locked loop (PLL) system generates the output serial data clock at 10x (standard definition) or 20x
(high definition) the parallel data clock frequency. This system consists of a VCO, dividers, phase-frequency
detector and internal loop filter. The VCO free-running frequency is internally set. The parallel data clock V
CLK
is
the reference for the PLL. The PLL automatically generates the appropriate frequency for the serial clock rate.
Loop filtering is internal to the LMH0030. The VCO has separate analog and digital power supply feeds: V
DDPLLA
pin 62, V
SSPLLA
pin 61, V
DDPLLD
pin 1, and V
SSPLLD
pin 2. These may be separately supplied power via external
low-pass filters, if desired. PLL acquisition time is less than 200µs @ 1485 Mbps. The VCO halts when the V
CLK
signal is not present or is inactive.
A LOCK DETECT indicator function is available as a bit in the VIDEO INFO 0 control registers. LOCK DETECT
is a logic-1 when the PLL is locked and a valid format has been detected. It can be assigned as an output on the
multifunction I/O port. By default LOCK DETECT is assigned as I/O Port bit 4 after power-on or reset . This
function also includes logic to check the stability of the device after the digital logic reset is released following
PLL lock. If the system is not fully stable, the logic is automatically reset. LOCK DETECT also combines the
function of indicating that the LMH0030 has detected the video format being received. This format detect function
involves determination of the major raster parameters such as line length, number of video lines in a frame, and
so forth. This is done so that information like line numbering can be correctly inserted. The PLL itself will have
locked in 200 microseconds (HD rates) or less. However, resolution of all raster parameters may take the
majority of a frame.
SERIAL DATA OUTPUT DRIVER
The serial data outputs provide low-skew complimentary or differential signals. The output buffer is a current-
mode design and is intended to drive AC-coupled and terminated, 75Ω coaxial cables. The driver automatically
adjusts its output slew rate depending upon the data rate being processed. Output levels are 800 mV
P-P
±10%
into 75Ω AC-coupled loads. The 75Ω resistors connected to the SDO outputs function both as drain-load and
back-matching resistors. Series back-matching resistors are not used with this output type.
The serial output level is controlled by the value of R
REF
LVL and R
REF
PRE connected to pin 53 and pin 52,
respectively. The R
REF
LVL resistor sets the peak-to-peak level of the output signal to the required SMPTE
nominal level. The R
REF
PRE resistor sets the value of a pre-emphasis current which is active during the
transition times of the HD-rate output signal. The value of R
REF
LVL is normally 4.75 KΩ, ±1%. The value of
R
REF
PRE is normally 4.75 KΩ, ±1%. The voltage present at these pins is approximately +1.3Vdc. The transition
times of this output buffer design automatically adjust and are different for the HD and SD data rate conditions.
The output buffer is quiescent when the device is in an out-of-lock condition. The output will become active after
the PLL is locked and a valid format has been detected. Separate power feeds are provided for the serial output
driver: V
SSSD
, pins 54, 55, and 59; V
DDSD
, pin 51; and V
DDLS
, pin 57.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMH0030