Datasheet

RD / WR
ANC / CTRL
ADDR DATA DATAADDR ADDR DATAAD[7:0]
WRITE
EXTERNAL BUS MUST
RELEASE
INTERNAL BUS WILL
RELEASE
ACLK
READ
READ
AD[9:8]
AD[9]
AD[8]
DRIVEN REC'D DRIVEN REC'D DRIVEN DRIVEN
AD[9]
AD[8]AD[8]
AD[9]
AD[8]
AD[9:8]
LMH0030
SNLS219G –JANUARY 2006–REVISED APRIL 2013 www.ti.com
Example: Read the Full-field Flags via the AD port.
1. Set ANC/CTRL to a logic-low.
2. Set RD/WR to a logic-high.
3. Present 001h to AD[9:0] as the register address.
4. Toggle ACLK.
5. Release the bus driving the AD port.
6. Read the data present on the AD port. The Full-field Flags are bits AD[4:0].
7. Toggle ACLK to release the AD port.
Figure 2. Control Data Read Timing (2 read and 1 write cycle shown)
CONTROL DATA WRITE FUNCTIONS
Figure 3 shows the sequence of clock and control signals for writing control data to the ancillary/control data port.
The control data write mode is similar to the read mode. The control data write mode is started by making both
the ANC/CTRL input low and the RD/WR input low. Next, the 8-bit address of the control register set to be
accessed is placed on port bits AD[7:0]. When a control register write address is being written to the port,
AD[9:8] must be driven as 00b (0XXh, where XX are AD[7:0]). Toggle ACLK. The address is captured on the
rising edge of ACLK. Remove the address after clocking it into the device on or before the falling edge of ACLK.
Observe the port input hold timing specification.
Next, the control register data is placed on the AD[7:0] port. ACLK is again toggled. The data is written to the
selected register on the rising edge of ACLK. When control data is being written to the port, AD[9:8] must be
driven as 11b (3XXh, where XX are AD[7:0]). Remove the register data after clocking it into the device on or
before the falling edge of ACLK. Observe the port input hold timing specification.
Example: Setup (without enabling) the TPG Mode via the AD port using the 1125 line, 30 frame, 74.25MHz,
interlaced component (SMPTE 274M) color bars as test pattern. The TPG may be enabled after setup using the
Multi-function I/O port or by the control registers.
1. Set ANC/CTRL to a logic-low.
2. Set RD/WR to a logic-low.
3. Present 00Dh to AD[9:0] as the Test 0 register address.
4. Toggle ACLK.
5. Present 327h to AD[9:0] as the register data.
6. Toggle ACLK.
12 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH0030