Datasheet

LMH0030
www.ti.com SNLS219G –JANUARY 2006–REVISED APRIL 2013
The SMPTE scrambler accepts 10-bit standard definition or 20-bit high definition parallel video data and
encodes it using the polynomial X
9
+ X
4
+ 1 as specified in the respective standard: SMPTE 259M, SMPTE
344M, or SMPTE 292M. The data is then serialized and sent to the NRZ-to-NRZI converter before being output.
The transmission bit order is LSB-first.
The NRZ-to-NRZI converter accepts NRZ serial data from the SMPTE scrambler. The data is converted to NRZI
format using the polynomial (X + 1). The converter's output goes to the output cable driver amplifier.
ANCILLARY/CONTROL DATA PATH
The 10-bit, bi-directional Ancillary and Control Data Port performs two distinct functions in the LMH0030. First,
it is used to selectively load ancillary data into the Ancillary Data FIFO for insertion into the video data stream.
The utilization and flow of ancillary data within the device is managed by a system of control bits, masks and IDs
in the control data registers. Second, this port provides read/write access to contents of the configuration and
control registers.
Ancillary and control data are input via the 10-bit Ancillary/Control Data Port, AD[9:0]. The state of the RD/WR
control input determines whether data is read or written to the registers or written to the Ancillary Data FIFO. The
state of the ANC/CTRL control input selects which of the ancillary data or control data sub-systems is accessed
through the port.
The ACLK input controls data flow through the port. The operation and frequency of ACLK is independent of the
video data clock, VCLK. However, the frequency of ACLK must be less than or equal to VCLK. There is no low
frequency limit for ACLK when it is being used for control register access. When theANC/CTRL input is a logic-
high, ACLK affects only the ancillary data FIFO operation. When the ANC/CTRL input is a logic-low, ACLK
affects only the control register operation.
Inputs AD[9:0], RD/WR and ANC/CTRL have internal pull down devices. ACLK does not have an internal pull
down device.
CONTROL DATA READ FUNCTIONS
Control data is written to and read from the LMH0030 using the lower-order 8 bits AD[7:0] of the
Ancillary/Control Data Port. This control data initializes, monitors and controls operation of the LMH0030. The
upper two bits AD[9:8] of the port are handshaking signals with the device accessing the port. AD[9:8] must be
driven as 00b (0XXh, where XX are AD[7:0]) when either a control register read or write address is being written
to the port. AD[9:8] must be driven as 11b (3XXh, where XX are AD[7:0]) when control data is being written to
the port. When control data is being read from the port, the LMH0030 will output AD[9:8] as 10b (2XXh, where
XX are output data AD[7:0]) and may be ignored by the monitoring system.
NOTE
When power is first applied to the device or after it is reset, the Ancillary and Control
Data Port must be initialized to receive data. This is done by toggling ACLK three (3)
times.
Figure 2 shows the sequence of clock and control signals for reading control data from the ancillary/control data
port. The Control Data Read mode is entered by making the ANC/CTRL input low and the RD/WR input high.
Next, the 8-bit address of the control register set to be accessed is placed on port bits AD[7:0]. When a control
register read address is being written to the port, AD[9:8] must be driven as 00b (0XXh, where XX are AD[7:0]).
ACLK is then toggled. The address is captured on the rising edge of ACLK. Observe the port input hold timing
specification.
Data from the selected register is driven by the port within a few nanoseconds immediately following the rising
edge of ACLK. To avoid contention with the port, the address driver should be turned off or tri-stated
immediately after the address is clocked into the device. Data may be read by external devices at any time after
the removal of the address signal. Output data will be driven until the next rising edge of ACLK. When the host
system finishes reading the data, toggle ACLK again. This second clock resets the port from drive to receive
mode and readies the port for another access cycle. When control data is being read from the port, the LMH0030
will output AD[9:8] as 10b (2XXh, where XX are output data AD[7:0]) and may be ignored by the monitoring
system.
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