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LMH0030

www.ti.com

SNLS219G –JANUARY 2006–REVISED APRIL 2013

LMH0030 SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs

and Integrated Cable Driver

Check for Samples: LMH0030

FEATURES

APPLICATIONS

• SDTV/HDTV Serial Digital Video Standard

• SDTV/HDTV Parallel-to-Serial Digital Video

Compliant Interfaces for:

• Supports 270 Mbps, 360 Mbps, 540 Mbps, – Video Cameras

1.4835Gbps and 1.485 Gbps SDV Data Rates

– VTRs

with Auto-Detection

– Telecines

• Low Output Jitter: 125ps max, 85ps typical

– Digital Video Routers and Switchers

• Low Power: Typically 430mW

– Digital Video Processing and Editing

• No External Serial Data Rate Setting or VCO

Equipment

Filtering Components Required*

– Video Test Pattern Generators and Digital

• Fast PLL Lock Time: < 150µs Typical at 1.485

Video Test Equipment

Gbps

– Video Signal Generators

• Adjustable Depth Video FIFO for Timing

Alignment

DESCRIPTION

• Built-in Self-Test (BIST) and Video Test Pattern

The LMH0030 SMPTE 292M/259M Digital Video

Generator (TPG)*

(1)

Serializer with Ancillary Data FIFO and Integrated

Cable Driver is a monolithic integrated circuit that

• Automatic EDH/CRC Word and Flag

encodes, serializes and transmits bit-parallel digital

Generation and Insertion

video data conforming to SMPTE 125M and 267M

• On-Chip Ancillary Data FIFO and Insertion

standard definition, 10-bit wide component video and

Control Circuitry

SMPTE 260M, 274M, 295M and 296M high-definition,

20-bit wide component video standards. The

• Flexible Control and Configuration I/O Port

LMH0030 operates at SMPTE 259M serial data rates

• LVCMOS Compatible Data and Control Inputs

of 270 Mbps, 360 Mbps, the SMPTE 344M serial data

and Outputs

rate of 540 Mbps, and the SMPTE 292M serial data

• 75Ω ECL-Compatible, Differential, Serial Cable-

rates of 1483.5 and 1.485 Gbps. The serial data clock

Driver Outputs

frequency is internally generated and requires no

external frequency setting, trimming or filtering

• 3.3V I/O Power Supply and 2.5V Logic Power

components.

Supply Operation

• 64-pin TQFP Package

(1) * Patent applications made or pending.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (37 pages)

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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 LMH0030 SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver Check for Samples: LMH0030 FEATURES APPLICATIONS • • 1 2 • • • • • • • • • • • • • • (1) SDTV/HDTV Serial Digital Video Standard Compliant Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.4835Gbps and 1.
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LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com DESCRIPTION (CONTINUED) The LMH0030 performs functions which include: parallel-to-serial data conversion, SMPTE standard data encoding, NRZ to NRZI data format conversion, serial data clock generation and encoding with the serial data, automatic video rate and format detection, ancillary data packet management and insertion, and serial data output driving.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 Block Diagram RESET RESET CONTROL BUILT-IN SELF-TEST & TEST PATTERN GENERATOR PCLK PCLK TRS & FORMAT DETECTOR DV[19:10] DV[9:0] INT.
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LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) It is anticipated that this device will not be offered in a military qualified version. CMOS I/O Supply Voltage (VDDIO–VSSIO): 4.0V SDO Supply Voltage (VDDSD–VSSSD): 4.
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LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com DC ELECTRICAL CHARACTERISTICS Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1) (2). Symbol Parameter Conditions Reference Min Max Units 2.0 VDDIO V VSSIO 0.8 V VIH Input Voltage High Level VIL Input Voltage Low Level IIH Input Current High Level VIH = VDDIO +90 +150 µA IIL Input Current Low Level VIL = VSSIO −1 −20 µA VOH CMOS Output Voltage High Level IOH = −6.6 mA 2.4 2.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 AC ELECTRICAL CHARACTERISTICS (continued) Over Supply Voltage and Operating Temperature ranges, unless otherwise specified(1).
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LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Test Loads VDDSD VDDIO 75: 1% IOL Hi-Z test eqpt. t 5k: (attenuation 0dB) S1 CMOS outputs 75: test eqpt. (attenuation 0dB) SDO SDO CL 1.0PF IOH CL S2 VDDSD CL including probe and jig capacitance, 3pF max. S1 - open, S2 - closed for VOH measurement S1 - closed, S2 - open for VOL measurement 75: 1% SDO SDO 1.0PF CL 5.5-30pF* 50: test eqpt. (attenuation 3.5dB) 24.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 Test Circuit +3.3 Vdc 4.7 PF 16V +2.5 Vdc 9 11 12 13 14 15 18 19 20 21 22 24 25 26 27 28 50 49 VDDIO VDDLS VDDSD VDDZ VDDPLLA VDDD IO0 IO1 3.3V Supply IO2 DV2 IO3 DV3 IO4 DV4 HD Chroma, SD Luma & Chroma DV5 IO5 IO6 DV6 IO7 DV7 ACLK DV8 AD0 DV9 AD1 DV10 AD2 LMH0030 DV11 AD3 DV12 AD4 DV13 AD5 DV14 AD6 HD Luma DV15 AD7 DV16 AD8 DV17 AD9 SDO DV19 SDO RREFLVL RD/WR RREFPRE 10, 17, 43 4 30 4.
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LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Timing Diagram 90% 90% VCLK (ACLK) 50% 10% tr, tf 10% tH tS 90% DV[19:0] (AD[9:0]) tr, tf 10% DEVICE OPERATION The LMH0030 SDTV/HDTV Serializer is used in digital video signal origination equipment: cameras, video tape recorders, telecines and video test and other equipment. It converts parallel SDTV or HDTV component digital video signals into serial format.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 The SMPTE scrambler accepts 10-bit standard definition or 20-bit high definition parallel video data and encodes it using the polynomial X9 + X4 + 1 as specified in the respective standard: SMPTE 259M, SMPTE 344M, or SMPTE 292M. The data is then serialized and sent to the NRZ-to-NRZI converter before being output. The transmission bit order is LSB-first. The NRZ-to-NRZI converter accepts NRZ serial data from the SMPTE scrambler.
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LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Example: Read the Full-field Flags via the AD port. 1. Set ANC/CTRL to a logic-low. 2. Set RD/WR to a logic-high. 3. Present 001h to AD[9:0] as the register address. 4. Toggle ACLK. 5. Release the bus driving the AD port. 6. Read the data present on the AD port. The Full-field Flags are bits AD[4:0]. 7. Toggle ACLK to release the AD port.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 ACLK RD/WR ANC/CTRL WRITE AD[7:0] ADDR AD[9] AD[9:8] DATA ADDR DATA AD[9:8] DRIVEN WRITE WRITE ADDR DATA AD[9] DRIVEN AD[8] AD[8] Figure 3. Control Data Write Timing ANCILLARY DATA FUNCTIONS The LMH0030 can multiplex Ancillary Data into the serial component video data stream. The ancillary data packet structure, formatting and control words are given in standard SMPTE 291M.
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LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com ACLK RD/WR ANC/CTRL WRITE AD[9:0] DATA DATA DATA DATA DATA DATA Figure 4. Ancillary Data Write Timing MULTI-FUNCTION I/O PORT The Multi-function I/O port can be configured to provide immediate access to many control and indicator functions within the LMH0030 configuration and control registers. The individual pins comprising this port may be assigned as input or output for selected bits in the control data registers.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 EDH/CRC SYSTEM The LMH0030 has EDH and CRC character generation and insertion circuitry. The EDH system functions as described in SMPTE Recommended Practice RP-165. The CRC system functions as specified in SMPTE 292M. The EDH/CRC polynomial generators accept parallel data from the input register and generate the EDH and CRC check words for insertion in the serial data.
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LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com CAUTION This output buffer is not designed or specified for driving 50Ω or other impedance loads. NOTE The SMPTE return loss specification is highly dependent on board design and can be challenging to meet with the LMH0030's integrated cable driver. In order to meet the SMPTE return loss specification, it is recommended to use an external cable driver such as the LMH0002 HD/SD SDI cable driver on the output of the LMH0030.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 The Pass/Fail bit in the TEST 0 control register indicates the test status. If no errors have been detected, this bit will be set to logic-1 approximately 2 field intervals after TPG Enable is set. If errors have been detected in the internal circuitry of the LMH0030, Pass/Fail will remain reset to a logic-0. The TPG or BIST is halted by resetting TPG Enable. The serial output data is present at the SDO outputs during TPG or BIST operation.
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LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Table 1.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 Table 2.
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LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Table 2.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 EDH REGISTERS 0, 1 AND 2 (Addresses 01h through 03h) Updated EDH packets may be inserted into the serial output data by setting the EDH Force bit in the control registers. The EDH Force control bit causes the insertion of new EDH checkwords and flags into the serial output regardless of the previous condition of EDH checkwords and flags in the input parallel data.
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LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com When ANC MASK[7:0] or ANC MASK[15:8] is set to FFh, packets with any DID, SDID or DBN can be loaded into the FIFO. When any bit or bits of ANC MASK[7:0] or ANC MASK[15:8] are set to a logic-1, the corresponding bit or bits of ANC ID[7:0] or ANC ID[15:8], respectively are a don't-care when matching IDs of incoming packets.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 The available formats and codes are detailed in Table 4. Generally speaking, the Format Set[4:0] codes indicate or group the formats as follows: Format Set[4] is set for the HD formats and reset for the SD formats. Format Set[3] when set indicates that PAL data is being processed. When reset NTSC data is being processed. Format Set[2:0] correspond to one of the sub-standards given in the table.
PAGE 24
LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com The TPG Enable bit when set to a logic-1 enables the Test Pattern Generator function and built-in self-test (BIST). This bit is mapped to I/O port bit 7 in the default condition. Note that the input pulldown on the I/O port bit has the effect of overriding the logic level of data being written into the register via the ancillary/Control Data Port.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 TEST MODE 0 REGISTER (Address 55h) The four bits of this register are intended for use as test mode functions. They are not normal operating modes. The bits may be set (enabled) or reset (disabled) by writing to the register. Reading this register sets (enables) all bits to their default ON condition. The Scrambler_Enable bit enables operation of the SMPTE scrambler function. This bit is normally ON.
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LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Table 5. Test Pattern Selection Codes(1) (continued) Test Pattern Select Word Bits > Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1125 Line, 74.25 MHz, 24 Frame Progressive Component (SMPTE 274M) Ref. Black 1 1 1 0 0 0 PLL Path. 1 1 1 0 0 1 EQ Path. 1 1 1 0 1 0 color Bars 1 1 1 0 1 1 750 Line, 74.25 MHz, 60 Frame Progressive Component (SMPTE 296M) Ref. Black 1 1 1 1 0 0 PLL Path. 1 1 1 1 0 1 EQ Path.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 Table 6. I/O Configuration Register Addresses for Control Register Functions Register Bit Bit Address Pin # SEL [n] I/P or O/P [5] [4] [3] [2] [1] [0] reserved 0 0 0 0 0 0 FF Flag Error 0 0 0 0 0 1 Output AP Flag Error 0 0 0 0 1 0 Output ANC Flag Error 0 0 0 0 1 1 Output CRC Error (SD/HD) 0 0 0 1 0 0 Output Power-On Status I/O Port Bit 5 Addresses x05h through x0Ch are reserved.
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LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com Table 6.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 PIN DESCRIPTIONS (1) Pin (1) Name Description 1 VDDPLLD Positive Power Supply Input (2.5V supply, PLL Logic) 2 VSSPLLD Negative Power Supply Input (2.
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LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS(1) (continued) Pin 30 Name Description 47 AD8 Ancillary/Control Data I/O Port 48 AD9 Ancillary/Control Data I/O Port 49 RD/WR Ancillary/Control Data Port Read/Write Control Input 50 ANC/CTRL Ancillary/Control Data Port Function Control Input 51 VDDSD Positive Power Supply Input (3.3V supply, Output Driver) 52 RREFPRE Output Preemphasis Reference Resistor (4.75 KΩ, 1% Nom.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 APPLICATION INFORMATION Complete details for the SD130ASM evaluation PCB are available on TI’s WEB site. This circuit demonstrates the capabilities of the LMH0030 and allows its evaluation in a native configuration. An assembled demonstration board kit, part number SD130EVK, complete with operating instructions, drawing package and list of materials is available.
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LMH0030 SNLS219G – JANUARY 2006 – REVISED APRIL 2013 www.ti.com PROCESSING NON-SUPPORTED AND pSf RASTER FORMATS The number and type of HD raster formats has proliferated greatly since the LMH0030 was designed. Though not specifically capable of fully or automatically processing these new formats, the LMH0030 may still be capable of serializing them.
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LMH0030 www.ti.com SNLS219G – JANUARY 2006 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision F (April 2013) to Revision G • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 3-Nov-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.