Datasheet

3.0 Applications Information
(Continued)
3.1 DESIGN EXAMPLE
In order to design a filter using the LMF100, we must define
the necessary values of three parameters for each
second-order section: f
0
, the filter section’s center frequency;
H
0
, the passband gain; and the filter’s Q. These are deter-
mined by the characteristics required of the filter being de-
signed.
As an example, let’s assume that a system requires a
fourth-order Chebyshev low-pass filter with 1 dB ripple, unity
gain at dc, and 1000 Hz cutoff frequency. As the system or-
der is four, it is realizable using both second-order sections
of an LMF100. Many filter design texts (and National’s
Switched Capacitor Filter Handbook) include tables that list
the characteristics (f
0
and Q) of each of the second-order fil-
ter sections needed to synthesize a given higher-order filter.
For the Chebyshev filter defined above, such a table yields
the following characteristics:
f
0A
= 529 Hz Q
A
= 0.785
f
0B
= 993 Hz Q
B
= 3.559
For unity gain at dc, we also specify:
H
0A
=1
H
0B
=1
The desired clock-to-cutoff-frequency ratio for the overall fil-
ter of this example is 100 and a 100 kHz clock signal is avail-
able. Note that the required center frequencies for the two
second-order sections will not be obtainable with
clock-to-center-frequency ratios of 50 or 100. It will be nec-
essary to adjust
externally. From Table 1 , we see that Mode 3 can be used to
produce a low-pass filter with resistor-adjustable center fre-
quency.
In most filter designs involving multiple second-order stages,
it is best to place the stages with lower Q values ahead of
stages with higher Q, especially when the higher Q is greater
than 0.707. This is due to the higher relative gain at the cen-
ter frequency of a higher-Q stage. Placing a stage with lower
Q ahead of a higher-Q stage will provide some attenuation at
the center frequency and thus help avoid clipping of signals
near this frequency. For this example, stage A has the lower
Q (0.785) so it will be placed ahead of the other stage.
For the first section, we begin the design by choosing a con-
venient value for the input resistance: R
1A
= 20k. The abso-
lute value of the passband gain H
OLPA
is made equal to 1 by
choosing R
4A
such that: R
4A
=−H
OLPA
R
1A
=R
1A
= 20k. If
the 50/100/CL pin is connected to mid-supply for nominal
100:1 clock-to-center-frequency ratio, we find R
2A
by:
The resistors for the second section are found in a similar
fashion:
The complete circuit is shown in Figure 19 for split
±
5V
power supplies. Supply bypass capacitors are highly
recommended.
LMF100
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