Datasheet

LM97593
SNWS019B –JULY 2007–REVISED APRIL 2013 www.ti.com
Figure 87. Isolating the ADC Clock from other Circuitry with a Clock Tree
Common Application Pitfalls
Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should
not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above
the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not
uncommon for high speed digital components (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot
that goes above the power supply or below ground. A resistor of about 47Ω to 100Ω in series with any offending
digital input, close to the signal source, will eliminate the problem.
Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or
power down.
Be careful not to overdrive the inputs of the LM97593 with a device that is powered from supplies outside the
range of the LM97593 supply. Such practice may lead to conversion inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must
charge for each conversion, the more instantaneous digital current flows through V
DR
and DRGND. These large
charging current spikes can couple into the analog circuitry, degrading dynamic performance. Adequate
bypassing and maintaining separate analog and digital areas on the pc board will reduce this problem.
The digital data outputs should be buffered (with 74ACQ541, for example) if they will drive a large capacitive
load. Dynamic performance can also be improved by adding series resistors at each digital output, close to the
LM97593, which reduces the energy coupled back into the part's output pins by limiting the output current. A
reasonable value for these resistors is 100Ω.
Using an inadequate amplifier to drive the analog input. As explained in Signal Inputs, the capacitance seen
at the input alternates between 8 pF and 7 pF, depending upon the phase of the clock. This dynamic load is
more difficult to drive than is a fixed capacitance. If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade performance. A small series resistor at each amplifier output
and a capacitor at the analog inputs will improve performance.
Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180º out of
phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will
affect the effective phase between these two signals. Remember that an operational amplifier operated in the
non-inverting configuration will exhibit more time delay than will the same device operating in the inverting
configuration.
Operating with the reference pins outside of the specified range. As mentioned in Reference Pins, V
REF
should be in the range of
0.8V ≤ V
REF
≤ 1.2V (15)
Operating outside of these limits could lead to performance degradation.
Inadequate network on Reference Bypass pins (V
RP
A, V
RN
A, V
COM
A, V
RP
B, V
RN
B and V
COM
B). As mentioned
in Reference Pins, these pins should be bypassed with 0.1 µF capacitors to ground at V
RM
A and V
RM
B and with
a 10 µF between pins V
RP
A and V
RN
A and between V
RP
B and V
RN
B for best performance.
Using a clock source with excessive jitter, using excessively long clock signal trace, or having other
signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive
output noise and a reduction in SNR and SINAD performance.
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