Datasheet

LM97593
www.ti.com SNWS019B –JULY 2007–REVISED APRIL 2013
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the
clock line as short as possible.
Digital circuits create substantial supply and ground current transients. The logic noise thus generated could
have significant impact upon system noise performance. The best logic family to use in systems with A/D
converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the
74LS, 74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that create the largest
supply current transients during clock or signal edges, like the 74F and the 74AC(T) families.
The effects of the noise generated from the LM97593 output switching can be minimized through the use of
100Ω resistors in series with each data output line. Locate these resistors as close to the LM97593 output pins
as possible.
Since digital switching transients are composed largely of high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area
is more important than is total ground plane volume.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in
high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to
keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the
generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause
problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to
degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.
Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the
signal path through all components should form a straight line wherever possible.
Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit
in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies
beside each other.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to
the reference input pin and ground should be connected to a very clean point in the ground plane.
All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed in the analog area of
the board. All digital circuitry and I/O lines should be placed in the digital area of the board. The LM97593 should
be between these two areas. Furthermore, all components in the reference circuitry and the input signal chain
that are connected to ground should be connected together with short traces and enter the ground plane at a
single, quiet point. All ground connections should have a low inductance path to ground.
DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. Isolate
the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 87. The gates used in
the clock tree must be capable of operating at frequencies much higher than those used if added jitter is to be
prevented.
Best performance will be obtained with a differential input drive, compared with a single-ended drive, as
discussed in Single-Ended Operation and Driving the Analog Inputs.
It is good practice to keep the clock line as short as possible and to keep it well away from any other signals.
Other signals can introduce jitter into the clock signal, which can lead to reduced SNR performance, and the
clock can introduce noise into other lines. Even lines with 90° crossings have capacitive coupling, so try to avoid
even these 90° crossings of the clock line.
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