Datasheet

3x2
8
2x2
8
1x2
8
0
0
4x2
8
5x2
8
6x2
8
7x2
8
8x2
8
INTEGRATOR OUTPUT
The min integrator
output must be
limited to 0 so that
the sign of AGAIN
is positive.
A GAIN
1
2
3
4
5
6
7
For this range to be
the same size as all
others, the max
integrator output must
be limited to 8x2
8
- 1 = 2
11
- 1
LM97593
www.ti.com SNWS019B –JULY 2007–REVISED APRIL 2013
The AGC may be forced to free run by setting AGC_HOLD_IC low. Writing an initial condition to AGC_IC_A|B
and then setting AGC_HOLD_IC high will force the AGC to a fixed gain. The three MSBs of the value written to
AGC_IC_A|B are inverted and output to drive the DVGA.
Allowing the AGC to free run should be appropriate for most applications. If the INH_EXP bit is not set, the
DVGA gain word (EXP) is routed to the “FLOAT TO FIXED CONVERTER” in the DDCs prior to the
programmable decimation filter. The EXP signals are delayed to account for the propagation delay of the DVGA
interface and the ADC12DL080 ADC.
Figure 85. AGC integrator output limits
General Applications Information
OUTPUTS
Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current flows through V
DR
and DRGND. These large charging
current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic
performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will
reduce this problem.
To minimize noise due to output switching, minimize the load currents at the digital outputs. Only one driven
input should be connected to each output pin. Additionally, inserting series resistors of about 100Ω at the digital
outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the
output currents, which could otherwise result in performance degradation. See Figure 86.
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