Datasheet
LM97593
www.ti.com
SNWS019B –JULY 2007–REVISED APRIL 2013
Register Name Width Type Default
(1)
Addr Bit Description
Selects internal node tap for debug.
0 selects F1 output for BI, 20 bits
1 selects F1 output for BQ, 20 bits
2 selects F1 output for AQ, 20 bits
3 selects F1 output for AI, 20 bits
4 selects F1 input for BI, 20 bits
5 selects F1 input for BQ, 20 bits
6 selects F1 input for AI, 20 bits
7 selects F1 input for AQ, 20 bits
8 selects NCO A, cosine output. 17 bits, 3 LSBs are 0.
DEBUG_TAP 5b R/W 0 31 5:1
9 selects NCO A, sine output, 17 bits, 3 LSBs are 0.
10 selects NCO B, cosine output, 17 bits, 3 LSBs are 0.
11 selects NCO B, sine output, 17 bits, 3 LSBs are 0.
12 selects NCO AI, rounded output, 15 bits, 5 LSBs are 0.
13 selects NCO AQ, rounded output, 15 bits, 5 LSBs are 0.
14 selects NCO BI, rounded output, 15 bits, 5 LSBs are 0.
15 selects NCO BQ, rounded output, 15 bits, 5 LSBs are 0.
16 selects AGC CIC filter output. 9 MSBs from ch A, next 9 bits
from ch B, 2 LSBs are 0.
17-31 Reserved.
DITH_A 1b R/W 1 31 6 0=Disable NCO dither source for channel A. 1=Enable.
DITH_B 1b R/W 1 31 7 0=Disable NCO dither source for channel B. 1=Enable.
RAM space that defines key AGC loop parameters. Format is 32
AGC_TABLE 32B R/W 0 128-159 7:0 separate 8-bit, 2’s complement numbers. This is common to both
channels.
Coefficients for F1. Format is 11 separate 16-bit, 2’s complement
numbers, each one spread across 2 registers. The LSBs are in
the lower registers. For example, coefficient h0[7:0] is in address
F1_COEFF 22B R/W 0 160-181 7:0
160, h0[15:8] is in address 161, h1[7:0] is in address 162,
h1[15:8] is in address 163. PAGE_SEL_F1=1 maps these
addresses to coefficient memory B.
Coefficients for F2. Format is 32 separate 16-bit, 2’s complement
numbers, each one spread across 2 registers. The LSBs are in
the lower registers. For example, coefficient h0[7:0] is in address
F2_COEFF 64B R/W 0 182-245 7:0
182, h0[15:8] is in address 183, h1[7:0] is in address 184,
h1[15:8] is in address 185. PAGE_SEL_F2=1 maps these
addresses to coefficient memory B.
Channel A F1 coefficient select register. 0=memory A, 1=memory
COEF_SEL_F1A 1b R/W 0 246 0
B.
Channel B F1 coefficient select register. 0=memory A, 1=memory
COEF_SEL_F1B 1b R/W 0 246 1
B.
PAGE_SEL_F1 1b R/W 0 246 2 F1 coefficient page select register. 0=memory A, 1=memory B.
Channel A F2 coefficient select register. 0=memory A, 1=memory
COEF_SEL_F2A 1b R/W 0 247 0
B.
Channel B F2 coefficient select register. 0=memory A, 1=memory
COEF_SEL_F2B 1b R/W 0 247 1
B.
PAGE_SEL_F2 1b R/W 0 247 2 F2 coefficient page select register. 0=memory A, 1=memory B.
0=SFS asserted at the start of each output word when
SFS_MODE 1b R/W 0 248 0 PACKED=1 or each I/Q pair when PACKED=0, 1=SFS asserted
at the start of each output sample period.
SDC_EN 1b R/W 0 248 1 0=normal serial mode, 1=serial daisy-chain master mode.
Enable reduced bandwidth AGC power detector. 0=2
nd
-order
AGC_COMB_ORD 2b R/W 0 249 1:0 decimate-by-eight CIC, 1=1-tap comb added to CIC, 2=4-tap
comb added to CIC.
Number of CK period delays needed to align the DVGA gain step
EXT_DELAY 5b R/W 0 249 6:2 with the digital gain compensation step. Set this register to 7 if
ASTROBE and BSTROBE are not used. Otherwise set to 8.
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